FDMS3620S Fairchild Semiconductor, FDMS3620S Datasheet

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FDMS3620S

Manufacturer Part Number
FDMS3620S
Description
This device includes two specialized N-Channel MOSFETs in a dual PQFN package
Manufacturer
Fairchild Semiconductor
Datasheet

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FDMS3620S
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FDMS3620S Rev.C
©2012 Fairchild Semiconductor Corporation
MOSFET Maximum Ratings
Thermal Characteristics
Package Marking and Ordering Information
FDMS3620S
PowerTrench
25V Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
Q2: N-Channel
V
V
I
E
P
T
R
R
R
D
J
DS
GS
AS
D
θJA
θJA
θJC
Max r
Max r
Max r
Max r
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
, T
Symbol
Device Marking
STG
DS(on)
DS(on)
DS(on)
DS(on)
08OD
06OD
= 4.7 mΩ at V
= 5.5 mΩ at V
= 1.0 mΩ at V
= 1.2 mΩ at V
Top
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
®
PowerStage
GS
GS
GS
GS
FDMS3620S
= 10 V, I
= 4.5 V, I
= 10 V, I
= 4.5 V, I
-Continuous (Silicon limited)
-Continuous
-Continuous (Package limited)
-Pulsed
Device
Power 56
Pin 1
D
D
D
D
= 17.5 A
= 38 A
= 16 A
= 35 A
T
A
= 25 °C unless otherwise noted
G2
Parameter
S2
S2
Pin 1
Power 56
Package
S2
PHASE
(S1/D2)
Bottom
1
G1
D1
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
D1
D1
D1
Reel Size
13 ”
T
T
T
T
T
C
C
A
A
A
(Note 4)
(Note 3)
= 25 °C
= 25 °C
= 25 °C
= 25 °C
= 25 °C
S2
S2
S2
G2
5
6
7
8
Tape Width
17.5
125
2.2
1.0
57
±12
12 mm
3.0
Q1
25
30
76
70
29
Q 2
1a
PHASE
1a
1c
1c
-55 to +150
1a
Q 1
120
2.5
1.0
38
50
±12
211
150
135
Q2
1.7
25
49
1b
1b
1b
1d
www.fairchildsemi.com
1d
3000 units
April 2012
Quantity
4
3
2
1
G1
D1
D1
D1
Units
°C/W
mJ
°C
W
V
V
A

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FDMS3620S Summary of contents

Page 1

... Package Marking and Ordering Information Device Marking Device 08OD FDMS3620S 06OD ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C General Description This device includes two specialized N-Channel MOSFETs 17.5 A dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous D buck converters ...

Page 2

... Q Total Gate Charge g Q Total Gate Charge g Q Gate to Source Gate Charge gs Q Gate to Drain “Miller” Charge gd ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev °C unless otherwise noted J Test Conditions = 250 μ mA 250 μ ...

Page 3

... 135 mJ is based on starting N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev °C unless otherwise noted J Test Conditions 17 ...

Page 4

... DUTY CYCLE = 0.5% MAX 150 0.5 1.0 1 GATE TO SOURCE VOLTAGE (V) GS Figure 5. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev 25°C unless otherwise noted J μ s 0.9 1.2 1 100 125 150 - 0.01 0.001 2 ...

Page 5

... MAX RATED 125 C/W θ 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 11. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev 25°C unless otherwise noted J 2000 1000 100 ...

Page 6

... Typical Characteristics (Q1 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 0.5 0.2 0.1 0.05 0.1 0.02 0.01 0.01 0.001 - Figure 13. ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev 25°C unless otherwise noted J SINGLE PULSE 125 C/W θ JA (Note 1b RECTANGULAR PULSE DURATION (sec) Junction-to-Ambient Transient Thermal Response Curve ...

Page 7

... 150 1.0 1.5 2 GATE TO SOURCE VOLTAGE (V) GS Figure 18. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev °C unless otherwise noted 2 μ s 0.6 0.9 Figure 15. Normalized on-Resistance vs Drain 50 75 100 125 150 200 100 ...

Page 8

... T = MAX RATED J 0 120 C/W θ 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 24. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev 25°C unless otherwise noted J 10000 100 120 100 125 ...

Page 9

... Typical Characteristics (Q2 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 0.0001 - Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev °C unless otherwise noted J SINGLE PULSE 120 C/W θ JA Note RECTANGULAR PULSE DURATION ( ...

Page 10

... TIME (ns) Figure 27. FDMS3620S SyncFET body diode reverse recovery characteristic ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C Schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. This will increase the power in the device ...

Page 11

... Dimensional Outline and Pad Layout 0. PKG PIN #1 IDENT MAY A PPEAR AS OPTIONAL 0.35 6X 3.90 3.70 0.58 0.38 0.44 0.24 0.10 C 0.08 C 1.10 0.90 ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C 5.10 4.90 A PKG 6. 5.90 2.15 4.16 2.13 0. VIEW 0.63 SEE DETAIL A RECOM MENDE D LAND PATTERN SIDE VIEW 0.10 3.00 0.58 0.70 0.05 0.38 2.80 0.50 1. 1.12 0.71 0.61 NOTES: UNLESS OTHERWIS E SPECIFIED 2 ...

Page 12

... Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C ® PowerTrench PowerXS™ SM Programmable Active Droop™ ® QFET QS™ Quiet Series™ RapidConfigure™ ™ ...

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