SAB C165-LM Infineon Technologies, SAB C165-LM Datasheet - Page 23

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SAB C165-LM

Manufacturer Part Number
SAB C165-LM
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAB C165-LM

Packages
PG-MQFP-100
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
2.0 KByte
Program Memory
0.0 KByte
The C165 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 4
time:
Table 4
Exception Condition
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
Class A Hardware Traps:
– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow
Class B Hardware Traps:
– Undefined Opcode
– Protected Instruction
– Illegal Word Operand
– Illegal Instruction
– Illegal External Bus
Reserved
Software Traps
– TRAP Instruction
Data Sheet
Fault
Access
Access
Access
shows all of the possible exceptions or error conditions that can arise during run-
Hardware Trap Summary
Trap
Flag
NMI
STKOF
STKUF
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
19
Vector
Location
00’0000
00’0000
00’0000
00’0008
00’0010
00’0018
00’0028
00’0028
00’0028
00’0028
00’0028
[2C
3C
Any
[00’0000
00’01FC
in steps
of 4
H
H
H
]
H
H
H
H
H
H
H
H
H
H
H
H
H
]
Trap
Number
00
00
00
02
04
06
0A
0A
0A
0A
0A
[0B
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
]
]
V2.0, 2000-12
Trap
Priority
III
III
III
II
II
II
I
I
I
I
I
Current
CPU
Priority
C165

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