SAB C165-LM Infineon Technologies, SAB C165-LM Datasheet - Page 44

• Manufacturer Part Number: SAB C165-LM
• Manufacturer: Infineon Technologies

Specifications of SAB C165-LM

• Packages: PG-MQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte

AC Characteristics
Definition of Internal Timing
The internal operation of the C165 is controlled by the internal CPU clock
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 9
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C165.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 9
generation mode.
Data Sheet
Direct Clock Drive
f
f
Prescaler Operation
f
f
OSC
CPU
OSC
CPU
associates the combinations of these three bits with the respective clock
Generation Mechanisms for the CPU Clock
f
CPU
can be generated from the oscillator clock signal
40
TCL
f
CPU
TCL
. This influence must
TCL
TCL
MCT04826
Figure
V2.0, 2000-12
f
CPU
f
OSC
. Both
C165
9).
via