S2050A AMCC (Applied Micro Circuits Corp), S2050A Datasheet

S2050A

Manufacturer Part Number

S2050A

Description

Manufacturer

AMCC (Applied Micro Circuits Corp)

Datasheet

1.S2050A.pdf (19 pages)

Specifications of S2050A

Case

QFP

99+

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DEVICE

SPECIFICATION

FEATURES

APPLICATIONS

High-speed data communications

Figure 1. System Block Diagram

March 29, 2000 / Revision B

BiCMOS PECL CLOCK GENERATOR

GIGABIT ETHERNET CHIPSET

• Functionally compliant with the 802.3z specification

• S2046 transmitter incorporates phase-locked

• S2050 receiver PLL configured for clock and

• 1250 Mbps (Gigabit Ethernet) operation

• 10- or 20-bit parallel TTL compatible interface

• +3.3/+5V power supply

• Low-jitter serial PECL compatible interface

• Lock detect

• Local loopback

• Compact 52 PQFP package

• Gigabit Ethernet framing performed by receiver

• Continuous downstream clocking from receiver

• TTL compatible outputs possible with +5V I/O

• Ethernet backbone connections

• Mainframe

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

• Proprietary extended backplanes

Controller

loop (PLL) providing clock synthesis from low-

speed reference

data recovery

power supply

Ethernet

Gigabit

S2050

S2046

Optical

GENERAL DESCRIPTION

The S2046 and S2050 transmitter and receiver pair

are designed to perform high-speed serial data trans-

mission over fiber optic or coaxial cable interfaces

conforming to the requirements of the proposed 802.3z

specification. The chipset is Gigabit Ethernet compli-

ant and supports 1250 Mbps with an associated 10

or 20-bit data word.

The chipset performs parallel-to-serial and serial-to-

parallel conversion and framing for block-encoded

data. The S2046 on-chip PLL synthesizes the high-

speed clock from a low-speed reference. The S2050

on-chip PLL synchronizes directly to incoming digital

signals, to receive the data stream. The transmitter

and receiver each support differential PECL-compat-

ible I/O for fiber optic component interfaces, to

minimize crosstalk and maximize data integrity. Local

loopback allows for system diagnostics. The I/O sec-

tion can operate from either a +3.3V or a +5V power

supply. (See Ordering Information .)

Figure 1 shows a typical network configuration incor-

porating the chipset.

Optical

S2046

S2050

S2046/S2050

Controller

Ethernet

Gigabit

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