MSC8101ADS Freescale Semiconductor / Motorola, MSC8101ADS Datasheet - Page 49

• Manufacturer Part Number: MSC8101ADS
• Description: MSC8101 APP DEV SYSTEM
• Manufacturer: Freescale Semiconductor / Motorola

2.6.4
The MSC8101 has several inputs to the reset logic:
Asserting an external
When the external
All these reset sources are fed into the reset controller, which takes different actions depending on the source of the
reset. The reset status register indicates the last sources to cause a reset. Table 2-12 describes reset causes.
2.6.4.1 Reset Operation
The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic
modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized
only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The
MSC8101 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration,
and reduced reset configuration.
Freescale Semiconductor
Input Clock
SPLL MF Clock
Bus/Output
Serial Communications Controller
Communications Processor Module
SC140 Core
Baud Rate Generator
•
•
•
•
Power-on reset
(PORESET)
Hard reset
(HRESET)
Soft reset
(SRESET)
For BRG DF = 4
For BRG DF = 16 (default)
For BRG DF = 64
For BRG DF = 256
•
•
•
•
•
•
•
Name
Power-on reset (
External hard reset (
External soft reset (
RSTCONF
DBREQ
HPE
BTM[0–1]
Reset Timing
—disable (0) or enable (1) the host port (HDI16)
Clock
—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1)
—boot from external memory (00) or the HDI16 (01)
—determines whether the MSC8101 is a master (0) or slave (1) device
PORESET
PORESET
Input/Output
Input/Output
Direction
PORESET
Input
SRESET
HRESET
signal is deasserted, the MSC8101 samples several configuration pins:
causes concurrent assertion of an internal
)
)
SPLLMFCLK
)
Symbol
CLKOUT
CPMCLK
BRGCLK
DSPCLK
PORESET initiates the power-on reset flow that resets all the MSC8101s and configures
various attributes of the MSC8101, including its clock mode.
The MSC8101 can detect an external assertion of HRESET only if it occurs while the
MSC8101 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-
drain pin.
The MSC8101 can detect an external assertion of SRESET only if it occurs while the
MSC8101 is not asserting reset. SRESET is an open-drain pin.
CLKIN
BCLK
SCLK
MSC8101 Technical Data, Rev. 19
Table 2-12.
Table 2-11.
562.5 KHz
2.25 MHz
18 MHz
18 MHz
18 MHz
35 MHz
70 MHz
72 MHz
36 MHz
9 MHz
Min
All
Clock Ranges
Reset Causes
Maximum Rated Core Frequency
166.7 MHz
20.83 MHz
250 MHz
83.3 MHz
83.3 MHz
83.3 MHz
5.21 MHz
250 MHz
1.3 MHz
Description
Max. Values for SC140 Clock Rating of:
31.25
83.3
PORESET
signal,
91.67 MHz
34.38 MHz
91.67 MHz
91.67 MHz
183.3 MHz
91.67 MHz
22.91 MHz
275 MHz
5.73 MHz
1.43 MHz
275 MHz
HRESET
, and
300 MHz
37.5 MHz
6.25 MHz
1.56 MHz
100 MHz
100 MHz
100 MHz
200 MHz
300 MHz
100 MHz
AC Timings
25 MHz
SRESET
2-9
.