MSC8101ADS Freescale Semiconductor / Motorola, MSC8101ADS Datasheet - Page 64

• Manufacturer Part Number: MSC8101ADS
• Description: MSC8101 APP DEV SYSTEM
• Manufacturer: Freescale Semiconductor / Motorola

Physical and Electrical Specifications
Note: The timing values refer to minimum system timing requirements. Actual implementation requires
2.6.8
2-24
No.
500
501
502
503
508
509
510
511
512
513
conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and
output signals associated with the referenced internal controllers and supported communication protocols.
For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling
mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of
signals; the direction (input or output) of some of the shared signal names depends on the selected mode.
JTAG Signals
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.6 V
TCK rise and fall times
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
Serial input clock
PIO/TIMER/DMA outputs
PIO/TIMER/DMA inputs
TDM outputs
Figure 2-23.
TDM inputs
Characteristics
Figure 2-22.
MSC8101 Technical Data, Rev. 19
DLLIN
Table 2-22.
PIO, Timer, and DMA Signal Diagram
22
20
TDM Signal Diagram
JTAG Timing
21
40
23
42
100.0
Min
25.0
12.5
40.0
0.0
0.0
6.0
3.0
0.0
0.0
All frequencies
Freescale Semiconductor
Max
40.0
15.0
20.0
3.0
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns