CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet
CS3410
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CS3410 Summary of contents
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... FEC related cores available from Amphion to rapidly construct complete FEC solutions. The Viterbi/TCM decoder operates in Viterbi or Trellis modes and provides a wide range of coding rates. The CS3410 is available in both ASIC and programmable logic versions that have been hand crafted by Amphion to deliver high performance while minimizing power consumption and silicon area. ...
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... PIN DESCRIPTION Table 1 provides the descriptions of the input and output ports of the CS3410 Viterbi/TCM decoder (shown graphically in Figure 2). Unless otherwise stated, all signals are active high and bit(0) is the least significant bit. Table 1: CS3410 - Viterbi/TCM Decoder Interface Signal Definitions Signal I/O Width (Bits) R0 ...
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... TCM mode is typically used for systems that are both power-limited and bandwidth- limited result, the CS3410 is well suited to many FEC Description Indicates synchronization update period – valid for one clock cycle. ...
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... CS3410 High Speed Viterbi/TCM Decoder Sync Control Sync Control R0 R1 Input Data R2 Interface R0ERASE R1ERASE R2ERASE CLK Status/Control µP Interface µP Interface Figure 3: Viterbi Decoder BLock Diagram Table 2: Input Data Format (Viterbi Mode) FSEL = 0 FSEL = 1 (Sign (Offset Magnitude) Binary) 1111 1111 ...
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Differential Decoder Differential Decoder block is required to eliminate ±180° phase ambiguities introduced by QPSK demodulation (assumes that input data to convolutional encoder has been differentially encoded). A bypass mode is also available. Sync Monitor Synchronisation monitor indicates the phase ...
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... Therefore, a configuration option is available for both the CS3310 and CS3410 to by pass differential encoder/decoder (Core Control register/ADD8). The CS3410 core is capable of de-puncturing both rate 1/2 and 1/3 symbol streams although its complementary encoder (CS3310) provides other rates, apart from rate 1/2 and 1/3, based upon a punctured 1/2 symbol stream ...
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... The effects of Pattern noise are minimized as paths to the correct (ideal) path converge after some history (or 'Traceback Length'). The YES CS3410 Decoder core has a 'Traceback length' of 170 memory YES and is more than adequate for other higher code rates. This maybe ...
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... Phase Ambiguity Encoding (and subsequent decoding) provides a mechanism to ensure the correct decoding of a data stream once it is known that a locked PSK state is rotated 'out- of-sync'. 'Sync Monitor' circuitry in CS3410 is used in conjunction with other circuit components to compensate for rotated phases. In addition, input and output differential ...
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... DESCRIPTION 0 This byte-wide interface allows the configuration of the 0000 15 CS3410 to be set by a microprocessor. Twelve 8-bit setup/ 1010 control registers are accessible through this interface (see Table 2). Address lines (ADD) select an 8-bit register for a read 1011 (RD) or write (WR) access. Write and read data are supplied ...
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... Bit Bit Bit Bit 15 10 Table 4: CS3410 Configuration Registers DATA BITS TPERIOD LS BYTE Bit 6 Bit 5 Bit 4 Bit 3 TPERIOD MS BYTE Bit 14 Bit 13 Bit 12 Bit 11 THRES LS BYTE Bit 6 Bit 5 Bit 4 Bit 3 THRES MS BYTE Bit 14 ...
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... BER count period value. Sets the range of an internal counter that is used to determine the error rate of the communications channel (Viterbi mode only). Normalization count period value. Sets the internal range of an internal counter that is used to determine the synchronization status of the CS3410 (using THRES). Threshold value is used in conjunction with accumulated-metric-normalization count (over TPERIOD) to ascertain synchronization status of CS3410. If the normalization count exceeds THRES then the core is deemed to be ‘ ...
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... Figure 15: TCM Mode Coding Performance Differential encoding/decoding marginally degrade (~0.2 dB) these gains. 12 ERROR CORRECTING PERFORMANCE The CS3410 demonstrates high coding gains in all modes of operation. In Viterbi mode a coding gain of 5 achievable in rate 1/3 and 5 rate 1/2 with a decoded BER of 10-5, as shown in Figure 14. In both TCM 2/3 and 3/4 modes coding gains of 3 ...
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... MICROPROCESSOR CONFIGURATION The microprocessor interface allows the configuration of the CS3410. Address lines (ADD) select an 8-bit register for a read (RD) or write (WR) access. Write and read data are supplied to/from CS3410 on the UP_DIN and UP_DOUT buses 254 respectively. To write to a register the WR signal must be set high with the associated address value on the ADD bus ...
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... High Speed Viterbi/TCM Decoder CONTINUOUS AND BLOCK MODE Continuous or Block Mode operation may be applied when CS3410 is configured in Viterbi or Trellis Mode. In Continuous Mode a high value on DVALI indicates valid input data. DVALO will go high 526 clock cycles (526 clock cycles = latency of the core) after DVALI has been clocked into the core ...
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CLK RESET DVALI BLKSTARTI BLKSTOPI DVALO BLKSTARTO BLKSTOPO DO Figure 20: Block Mode Operation PHASE SYNCHRONIZATION In both Viterbi and TCM modes of operation, an 'out-of-sync' condition occurs when a tracked internal path metric state (most likely ...
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... CS3410 High Speed Viterbi/TCM Decoder "Normalisation" BLKSTARTI BLKSTOPO Sync Monitor DVALI CLK Figure 21: Sync Monitor Figure 21 conceptually illustrates the Sync Monitor circuitry used to phase lock 'out-of-sync' states. When both BLK and SBD signals are high, the Sync Monitor circuitry operates in a burst mode fashion ...
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CLK BLKSTOPO SYNCS OSYNC SYNCUP BLKERR Figure 24: ‘Out-of-Sync’ Burst Dependent Phase Lock Monitoring CLK BLKSTOPO SYNCS OSYNC SYNCUP BLKERR Figure 25: ‘In-sync’ Burst Independent Phase Lock Monitoring CLK BLKSTOPO SYNCS OSYNC SYNCUP BLKERR Figure 26: ‘Out-of-’sync’ Burst Independent Phase ...
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... CS3410 High Speed Viterbi/TCM Decoder BER Estimation BER, a microprocessor register value, contains an estimation of the communications channel bit error rate in Viterbi mode only. A BER monitor is employed to provide this value at an interval defined by BPERIOD. Figure 27 describes the BER Monitor circuitry. Delay Compare Error Counter ...
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... For applications that require the high performance, low cost and high integration of an ASIC, Amphion delivers the ASIC Core series of multimedia ASVCs that are pre-optimized to a targeted silicon technology by Amphion experts. Choose from off-the- shelf versions of the CS3410 available for many popular ASIC and foundry silicon supplier technologies or Amphion can port the CS3410 to a technology of your choice. ...
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... CS3410 High Speed Viterbi/TCM Decoder ABOUT AMPHION Amphion (formerly Integrated Silicon Systems) is the leading supplier of speech coding, video/ image processing and channel coding ASVCs for system-on-a-chip (SoC) solutions in the telecommunications/ Internet, consumer / communications and wireless markets. Web: www.amphion.com Email: info@amphion.com ...