CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet - Page 7

• Manufacturer Part Number: CS3410
• Description: High Speed Viterbi/TCM Decoder
• Manufacturer: Amphion Semiconductor Ltd.

Figure 9: IQ Rotation Pattern
Automatic protection from a ±180° phase ambiguity is
available through the use of onboard differential encoding/
decoding blocks (if enabled). The detection of ±90° phase
ambiguities is deterministic and can only be reliably judged
using the Decoders built-in statistical monitoring circuitry.
This case is explained in more detail in Phase Synchronization
section.
Table 3 summarizes the methods by which a Viterbi mode of
operation may lose synchronization.
Data Interface Pattern refers to the input I/Q data sequence of
the core illustrated in Figure 8. Therefore, it is evident that in
the case of Viterbi rate 1/3, the core may incorrectly lock onto a
receive sequence, such as Q/I/Q instead I/Q/I. Also if the
received I/Q data sequence is rotated as shown in Figure 8 a
vector swap and single vector inversion is required to correct
it. Therefore, the built-in data interface in conjunction with the
cores Sync Monitor circuitry, is capable of resolving these
issues.
Table 3: Phase Synchronization Dependence
Viterbi
Rate
1/2
1/3
Q
Q
Q
Data Interface
(I, Q)
(I, Q)
(I, Q)
Pattern
YES
–180
+90
→
→
→
-90
I
I
-
I
o
(-Q, I)
(-I, -Q)
o
(Q, -I)
o
-Q
-I
I
IQ Rotation
Pattern
YES
YES
-Q
Q
-I
Note:
longer than that of the Viterbi rate 1/2 configuration.
The following list summarizes the capability of the Decoders
input data interface to handle the issues described above:
•
•
Viterbi decoding consists of 3 main steps: Branch Metric (BM)
Calculation, Trellis Computation, and Traceback.
Branch Metric (BM) Calculation
This indicates the correlation between the received code
words and all possible code word combinations. Computed
BM values are fed into a 64-state Add Compare Select (ACS)
block that represents the trellis structure applicable to this
core. The decoder determines the state of the encoder using a
maximum likelihood technique. The value of the encoder
memory is determined as its previous state is already known.
For each ACS state, a winning BM value is accumulated in a
Path Metric (PM) register.
Trellis Computation
To determine the encoder state, the PM state is monitored for
the occurrence probability for each of the 64 possible encoder
memory states. As Path Metrics are computed, a binary
decision is formed for each of the possible trellis states, thus
determining the probable path taken to arrive at a particular
state. These binary decisions are stored in 'Decision' memory.
Traceback
Decoded output data is formed from following the path of the
current state to a finite past state whilst monitoring the
appropriate state transition for each iteration. The effects of
noise are minimized as paths to the correct (ideal) path
converge after some history (or 'Traceback Length'). The
CS3410 Decoder core has a 'Traceback length' of 170 memory
and is more than adequate for other higher code rates.
Provision of an input data buffer for Viterbi 1/3 modes
where output symbols are shared across subsequent
QPSK transmissions.
A "swap-and-invert" function to correct for ±90° phase
ambiguities.
automatically when the core is deemed 'out-of-sync'.
Viterbi rate 1/3 phase synchronization may take 1.5x
This
maybe
triggered
manually
or
7
TM