CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet - Page 18

• Manufacturer Part Number: CS3410
• Description: High Speed Viterbi/TCM Decoder
• Manufacturer: Amphion Semiconductor Ltd.

BER Estimation
BER, a microprocessor register value, contains an estimation
of the communications channel bit error rate in Viterbi mode
only. A BER monitor is employed to provide this value at an
interval defined by BPERIOD. Figure 27 describes the BER
Monitor circuitry.
Figure 27: BER Monitor
Input hard decisions bits (MSB's of R0/R1/R2) are delayed by
the latency of the Viterbi decoder core to coincide with the re-
encoded decoded Viterbi bit. A mismatch in these values
indicates a channel bit error. This bit error is counted over a
period defined by the microprocessor register BPERIOD. This
value is accumulated during the active state of a BPERIOD
Figure 28: BER Register Update
18
Decoded
CS3410
Viterbi
Bit
Delay
HD
BERDONE
BER
CLK
Viterbi Encoder
Compare
High Speed Viterbi/TCM Decoder
Error Counter
BER (µP Interface)
BERDONE
counter that is incremented on every CLK cycle during
DVALO signal. Once the BPERIOD counter has reached the
BPERIOD value, the accumulated bit error value is made
available to the microprocessor interface. The BERDONE flag
indicates that BER has been updated as shown in Figure 28.
It should be noted that the BPERIOD counter is a modulo type
that is free running during all active DVALO intervals and is
not reset between bursts. The minimum count value is 1024
cycles
(BPERIOD+1)*1024 cycles during DVALO. The maximum
count value available from the 16-bit BPERIOD register is
67.1E6 cycles. The BER of the channel is simply the number of
accumulated error mismatches divided by the time period
defined by BPERIOD and CLK. This value should be
determined/calibrated externally as the BER register only
contains the accumulated error count value for that period. It
should be noted that the BER of the communications channel
approximately equals the BER of the complete system since
the probability of the decoder incorrectly decoding a bit is at
least two orders of magnitude below the probability of a
channel bit error.
with
BPERIOD
=
0,
i.e.
count
period
=