A43L0616V-8 AMIC Technology, Corp., A43L0616V-8 Datasheet - Page 19

• Manufacturer Part Number: A43L0616V-8
• Description: 512K x 16 Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

5. Write Interrupted by Precharge & DQM
Note : 1. To inhibit invalid write, DQM should be issued.
6. Precharge
7. Auto Precharge
(October, 1999, Version 0.0)
* Note : 1. Number of valid output data after Row Precharge : 1,2 for CAS Latency = 2,3 respectively.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
DQ(CL2)
DQ(CL3)
2. The row active command of the precharge bank can be issued after tRP from this point.
DQ(CL2)
DQ(CL3)
1) Normal Write (BL=4)
1) Normal Write (BL=4)
2) Read (BL=4)
2) Read (BL=4)
The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge,
CMD
DQM
CLK
DQ
CMD
CMD
CMD
CMD
CLK
CLK
DQ
DQ
CLK
CLK
WR
D0
WR
D0
WR
D0
RD
RD
D1
D1
D1
D2
D2
D2
Q0
Q0
PRE
D3
D3
D3
Q0
Q0
Q1
Q1
Masked by DQM
t
Note 1
RDL
Note 2
Note 1
Auto Precharge Starts
Auto Precharge Starts
PRE
PRE
Q1
Q1
Q2
Q2
CAS
Q2
Q2
Q3
Q3
Note 2
Note 2
interrupt of the same/another bank is illegal.
18
1
Note 2
Q3
Q3
2
AMIC Technology, Inc.
A43L0616