CS6150 Amphion Semiconductor Ltd., CS6150 Datasheet - Page 11

• Manufacturer Part Number: CS6150
• Description: Motion JPEG Decoder
• Manufacturer: Amphion Semiconductor Ltd.

Most inputs and outputs to the CS6150 are registered and fully synchronous. Full pin descriptions and conditional timing
behavior for non-registered pins is given in the CS6150 databook. Example timing characteristics for the CS6150 are given
in Table 7. Timing characteristics are technology dependent and will vary by instantiation as signal loading in the target system
determines final timing.
For ASIC prototyping or for projects requiring the fast time to market of a programmable logic solution, Amphion's Celerity Core
solutions offer the silicon-aware performance tuning found in all Amphion products, combined with the rapid design times
offered by today’s leading programmable logic solutions.
CSO6150TK: All values reflect pre-layout estimated timing. Wireloading conditions use "Conservative" model supplied by library vendor and worst case commercial
Table 7: Decoder Timing Characteristics
* Performance figures based on silicon vendor design kit information. ASIC performance is pre-layout using vendor-provided statistical wire loading information under the following
** Logic gates do not include clock circuitry.
Consult your local AMPHION representative for product specific performance information, current availability of individual products, and lead times on Optima core porting.
Table 8: Optima Cores
* Performance represents core only under worst case commercial conditions. Does not include timing effect of external logic and I/O circuitry.
Table 9: Celerity Cores
For applications that require the high performance, low cost and high integration of an ASIC, Amphion delivers the Optima
Cores series of multimedia ASVCs that are pre-optimized by Amphion experts to a targeted silicon technology. Choose from
off-the-shelf versions of the CSO6150 available for many popular ASIC and foundry silicon supplier technologies, or Amphion
can port the CSO6150 to a technology of your choice.
conditions: (T J = 125°C, V
CSO6150TK
CSO6150KJ
PRODUCT
PRODUCT ID#
CSO6150
CSC6150AA
CSC6150AA
ID#
SYMBOL
t skew
t cyc
t co
t su
t h
operating conditions.
VENDOR
SILICON
CC
VENDOR
SILICON
AVAILABILITY AND IMPLEMENTATION INFORMATION
Amkor
TSMC
Altera
-10% ).
Xilinx
Input port set-up time
Input port hold time
Output port clock
DESCRIPTION
Clock Cycle Rate
PROGRAMMABLE
to output timing
LOGIC PRODUCT
Apex 20KE FPGA
0.25-micron using Synopsys
Virtex-E FPGA
Clock skew
0.18-micron using Artisan
standard cell libraries
standard cell libraries
NAME/PROCESS
Decoder - ASIC
Baseline JPEG
PRODUCT
TIMING CHARACTERISTICS
CELERITY
OPTIMA
PERFORMANCE*
(MSAMPLES/SEC)
26
28
PERFORMANCE*
CONDITION
(Msamples/sec)
™
Worst case
™
CORES
max
max
max
max
CORES
125
95
DEVICE RESOURCES
USED (LOGIC
4466 slices
9433 LEs
GATES**
LOGIC
)
72k
71k
VALUE
200 ps
8.0 ns
2.8 ns
2.8 ns
0 ns
DEVICE RESOURCES
USED (MEMORY
5 block RAMs
MEMORY
0.31mm
0.57mm
17 ESB
AREA
Synthesis Value, final skew
Positive edge triggered
All registered outputs
2
2
is design dependent
COMMENT
)
AVAILABILITY
Porting Available
AVAILABILITY
Now
Now
Now
Now
Now
11