A45L9332AE-6 AMIC Technology, Corp., A45L9332AE-6 Datasheet - Page 12

• Manufacturer Part Number: A45L9332AE-6
• Description: 256K x 32 Bit x 2 Banks Synchronous Graphic RAM
• Manufacturer: AMIC Technology, Corp.

Simplified Truth Table
SGRAM vs SDRAM
IF DSF is low, SGRAM functionality is identical to SDRAM functionality.
SGRAM can be used as an unified memory by the appropriate DSF control
PRELIMINARY
SDRAM = Graphic Memory + main Memory
Function
Function
SGRAM
DSF
4. A10 : Bank select address.
5. It is determined at Row active cycle.
6. During burst read or write with auto precharge, new read/ (block) write command cannot be issued.
7. Burst stop command is valid only t full page burst length.
8. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
9. Graphic features added to SDRAM’s original features.
If “Low” at read, (block) write, Row active and precharge, bank A is selected.
If “High” at read, (block) write, Row active and precharge, bank B is selected.
If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit = I/O mask
Another bank read/(block) write command can be issued at t
but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ’s.
(October, 2001, Version 0.1)
(Block) Write with write per bit mode = Masked (Block ) Write
MRS
L
MRS
SMRS
H
Write per bit
Bank Active
Disable
with
11
L
Bank Active
PR
after the end of burst.
Write per bit
Bank Active
Enable
with
H
AMIC Technology, Inc.
A45L9332A Series
Normal
Write
L
Write
Block
Write
H