RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 265

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
NOTE:
11.5 Burst FIFO Buffers
Two small FIFO buffers are implemented to support PCI burst-mode operation, to
allow synchronization between the RS8234 internal logic and the PCI bus
interface, and to carry commands from the DMA coprocessor to the PCI bus
logic. The incoming FIFO is 512 x 32 bits, the outgoing FIFO is 16 x 36 bits.
4.
5.
Interface Disabled—If the driver or application software on the PCI host
CPU has disabled, the RS8234 PCI bus master logic (using the M_EN bit
in the Command field of the PCI bus configuration registers), then any
attempt to perform a DMA transaction to the PCI bus will result in an
error. In this case, the MERROR and INTF_DIS bits in the PCI
configuration space will be set and the PCI_BUS_STATUS[1] bit in the
SYS_STAT Register will be set.
Internal Failure—Upon a synchronization error between the DMA
coprocessor and the PCI master logic, an internal failure will be flagged. In
this case, the MERROR and INT_FAIL bits in the PCI configuration space
will be set and the PCI_BUS_STATUS[0] bit in the SYS_STAT Register
will be set.
The above errors permanently affect system level operation. Because of
this the system should be re-initialized, since full system level recovery is
unlikely. The bus protocol errors can be cleared either by a software reset
of the associated status flag or flags, i.e., RTA, RMA, or DPR, or with a
reset of the PCI bus master logic using the HRST* input pin. For example,
a master abort error can be cleared by writing a logic one to the RMA
status bit in the PCI Configuration Register space, causing the status bit to
be cleared. Internal failures (attempting to initiate a master transaction
with the interface disabled, or loss of synchronization with the DMA
controller) can only be reset by applying the global reset, CONFIG0
(GLOBAL_RESET), or by asserting the HRST* signal.
Configuration Register drives the PCI_BUS_ERROR interrupt. To clear
this interrupt, a logic high must be written to the MERROR bit location.
The MERROR bit can also be cleared by a logic low on the HRST* input
pin.
(PCI_ERR_RESET) to a logic high. After the errors have been cleared, the
SAR should be re-initialized.
recovering from a PCI master error. The PCI host software can determine
that an error occurred by checking the MERROR bit. It can also determine
if the transaction was a read or write by inspecting the MRD bit, and then
retrieve the read or write address at which an error occurred by reading the
MASTER_READ_ADDR or MASTER_WRITE_ADDR fields.
block are under the control of the PCI_READ_MULTI bit in the
CONFIG0 register.
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Next, the MERROR bit must be cleared. The MERROR bit in the PCI
The local processor can clear the error bits by setting CONFIG0
Several fields are provided in the PCI configuration space to aid in
The PCI Read and PCI Read MULTIPLE commands issued by the PCI
™
11.0 PCI Bus Interface
11.5 Burst FIFO Buffers
11-5