RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 305

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
0x16c - AAL5 PDUs Discarded Counter (AAL5_DSC_CNT)
This register counts the number of AAL5 CPCS-PDUs discarded due to buffer firewall, buffer underflow, or
status overflow. The counter is reset to zero by an assertion of either the HRST* system reset pin or the
GLOBAL_RESET bit in the CONFIG0 register. Optionally, an interrupt can be programmed when the counter
rolls over.
0x1a0 - Host Mailbox Register (HOST_MBOX)
This register implements a mailbox for communication between the host and local processors. The register is
written by the local processor and read by the host to pass messages in that direction. Writes to this register may
interrupt the host while reads can interrupt the local processor.
0x1a4 - Host Status Write Register (HOST_ST_WR)
This register indicates if a reassembly or segmentation host-located status queue has been written. Only queues
0 through 15 are supported. All bits are latched until read by the host. The RSM_HS_WRITE[15:0] bits are
ORed together into HOST/LP_ISTAT0(RSM_HS_WRITE), and the SEG_HW_WRITE[15:0] bits are ORed
together into HOST/LP_ISTAT0(SEG_HS_WRITE).
0x1b0 - Local Processor Mailbox Register (LP_MBOX)
This register implements a mailbox for communication between the host and local processors. LP_MBOX is
written by the host processor and read by the local processor to pass messages in that direction. Writes to this
register can interrupt the local processor while reads can interrupt the host processor.
28234-DSH-001-B
31–16
31-16
31–0
15-0
15-0
Bit
Bit
Bit
Field
Field
Field
Size
Size
Size
16
16
32
16
16
Reserved
AAL5_DSC_CNT
HOST_MBOX[31:0]
RSM_HS_WRITE[15:0]
SEG_HS_WRITE[15:0]
Name
Name
Name
Mindspeed Technologies
Not implemented at this time.
AAL5 PDUs discarded by the reassembly coprocessor.
Messages flow from local processor to host.
Indication that a host-located reassembly status queue entry has
been written. Only queues 0 through 15 are supported.
Indication that a host-located segmentation status queue entry has
been written. Only queues 0 through 15 are supported.
™
Description
Description
Description
13.6 Counters and Status Registers
13.0 RS8234 Registers
13-23