RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 275

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Figure 12-2. Transmit Timing in UTOPIA Mode with Cell Handshake
28234-DSH-001-B
TXD/TXPAR
NOTE(S):
(1)
(2)
(3)
(4)
TXSOC
FRCTRL
Once transfer of a cell is started, TxClav is sampled only on the last octet of a cell.
TxEN* goes active if TxClav is inactive at previous rising clock edge and a complete cell in the transmit FIFO buffer.
TxEN* goes inactive due to TxClav being active on previous cycle.
TxEN* goes inactive since a complete cell is not in the transmit FIFO buffer.
TXCLAV
TXEN*
(2)
H1
***
CLKD3 output; a 50% duty cycle clock derived by dividing CLK2X by three.
In UTOPIA mode, the FRCTRL input can be connected to the RS8234
P44
Mindspeed Technologies
P45
P46
P47
P48
(1)
™
12.4 UTOPIA Mode Cell Handshake Timing
X
(3)
H1
12.0 ATM Utopia Interface
***
P48
(4)
X
100074_081
12-5