S1D13700F01 Epson Electronics America, Inc., S1D13700F01 Datasheet - Page 106

• Manufacturer Part Number: S1D13700F01
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 106
S1D13700F01
X42A-A-002-04
No.
4
5
6
HDOT SCR
Command
P10 = 30h
P3 = 07h
P4 = 3Fh
P5 = 49h
P6 = 7Fh
P7 = 80h
P8 = 00h
SCROLL
P1 = 00h
P2 = 00h
P3 = 40h
P4 = 00h
P5 = 10h
P6 = 40h
P7 = 00h
P8 = 04h
P9 = 00h
P1 = 00h
P1 = 01h
C = 5Ah
C = 5Bh
C = 44h
OVLAY
Table 15-2 Indirect Addressing Initialization Procedure (Continued)
FY: Vertical character size = 8 pixels (REG[02h] bits 3-0
C/R: 64 display addresses per line (REG[03h] bits 7-0)
TC/R: Total address range per line = 90 (REG[04h] bits 7-0)
fOSC = 6.5 MHz, fFR = 70 Hz
L/F: 128 display lines (REG[05h] bits 7-0
AP: Virtual screen horizontal size is 128 addresses (REG[06h] bits 7-0, REG[07h]
bits 7-0)
First screen block start address (REG[0Bh] bits 7-0, REG[0Ch] bits 7-0)
Set to 0000h
Display lines in first screen block = 64 (REG[0Dh] bits 7-0)
Second screen block start address (REG[0Eh] bits 7-0, REG[0Fh] bits 7-0)
Set to 1000h
Display lines in second screen block = 64 (REG[10h] bits 7-0)
Third screen block start address (REG[11h] bits 7-0, REG[12h] bits 7-0)
Set to 0400h
Fourth screen block start address (REG[13h] bits 7-0, REG[14h] bits 7-0)
Set to 3000h
Set horizontal pixel shift to zero (REG[1Bh] bits 2-0)
MX 1, MX 0: Inverse video superposition (REG[18h] bits 1-0)
DM 1: First screen block is text mode (REG[18h] bit 2)
DM 2: Third screen block is text mode (REG[18h] bit 3)
(SAD1) 0000h
(SAD3) 0400h
(SAD2) 1000h
(SAD4) 3000h
0800h
5000h
Display memory
Revision 4.05
1st display memory page
2nd display memory page
3rd display memory page
4th display memory page
Operation
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2005/12/13