S1D13700F01 Epson Electronics America, Inc., S1D13700F01 Datasheet - Page 83

• Manufacturer Part Number: S1D13700F01
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
12.2.3 Display Scan Timing
Hardware Functional Specification
Issue Date: 2005/12/13
Frame
Period
Figure 12-7 Relationship Between Total Character Bytes Per Row and Character Bytes Per Row
Where:
C/R = character bytes per row (REG[03h] bits 7-0)
TC/R = total character bytes per row (REG[04h] bits 7-0)
L/F = frame height in lines (REG[05h] bits 7-0)
Note
Note
During display scanning, the S1D13700F01 pauses at the end of each line for TC/R - C/R
((REG[04h] bits 7-0) - (REG[03h] bits 7-0)) display memory read cycles, although the
LCD drive signals are still generated. TC/R may be set to any value within the constraints
imposed by C/R, Input Clock (CLK), f
be used to fine tune the frame frequency.
In text mode (when the CGROM or CGRAM is used), it is recommended that the micro-
processor access the memory only during the pause at the end of each line (see Section
7.3.6, “Display Memory Access Timing for Text Mode” on page 36). Otherwise, flick-
ering on the display may result during memory accesses.
For graphics mode, memory can be accessed at any time.
The divider adjustment interval (R) applies to both the upper and lower screens even if a
dual panel drive is selected, REG[00h] bit 3 = 1. In this case, FPLINE is active only at
the end of the lower screen’s display interval.
FPLINE
Line 1
L/F
2
3
Revision 4.05
Display Period
C/R
FR
O
O
O
O
•
•
•
•
•
, and the size of the LCD panel. This pause may
TC/R
Divider Frequency
Period
R
R
R
R
X42A-A-002-04
S1D13700F01
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