S1D13700F01 Epson Electronics America, Inc., S1D13700F01 Datasheet - Page 133

• Manufacturer Part Number: S1D13700F01
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
X42A-A-001-01
X42A-A-001-01
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2005/12/13
• section 10.3.4, added note about gray scale only available for layer 1
• section 11.1.2, changed bit 3 value from 01 to 0
• section 15.1.1, updated formulas for 1, 2, 4 bpp in system set section
• table 15-1, changed TC/R value for 256x64 from 24h to 2Eh
• table 15-1, changed TC/R value for 256x128 from 16h to 24h
• released as revision 1.0
• started from S1D13700F00 Hardware Specification (X42A-A-001-xx)
• section 7.3, removed parameters t12, t13, t14 from the timing diagrams/tables with
• section 7.3.3, changed references in the timing table from “WAIT#” to “DTACK#”
• section 7.3.5, removed note about CLK input under the M6800 diagram
• table 9-1, for parameter Rd, typical is 100ohm not 100Kohm
• REG[00h] bit 0, added note about 1bpp only when CGRAM is used
• REG[0Bh] - REG[0Ch], added note about programming the LSB before the MSB
• REG[0Eh] - REG[0Fh], added note about programming the LSB before the MSB
• REG[11h] - REG[12h], added note about programming the LSB before the MSB
• REG[13h] - REG[14h], added note about programming the LSB before the MSB
• REG[20h], added information about 1bpp only when CGRAM is used
• section 15.1.5, removed note about line noise during three layer graphics mode
• section 13.1.3, added note about 1bpp only when CGRAM is used
• section 13.3, added note about 1bpp only when CGRAM is used
• section 15.1.1, updated TC/R’ formulas for 1 Bpp and 2 Bpp
• section 19, added reference to the Product Brief
Revision 1.01
Revision 1.0
Revision 0.01
WAIT#/DTACK#
Revision 4.05
X42A-A-002-04
S1D13700F01
Page 133