CDK1307 Cadeka Microcircuits LLC., CDK1307 Datasheet - Page 10

• Manufacturer Part Number: CDK1307
• Description: 12/13-bit Analog-to-digital Converters Adcs
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
©2009 CADEKA Microcircuits LLC
Symbol
Clock Inputs
Timing
Logic Inputs
Logic Outputs
T
T
T
T
ε
T
T
T
V
V
I
I
C
V
V
C
IH
IL
PD
SLP
OVR
AP
RMS
LAT
D
DC
IH
IL
I
OH
OL
L
and resulting switching noise at a minimum.
Parameter
Duty Cycle
Compliance
Input Range
Input Common Mode Voltage
Input Capacitance
Start Up Time from Power Down
Start Up Time from Sleep
Out Of Range Recovery Time
Aperture Delay
Aperture Jitter
Pipeline Delay
Output Delay
Output Delay Relative to CLK_EXT
High Level Input Voltage
Low Level Input Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Max Capacitive Load
Conditions
Differential input swing
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of OV
Differential
From Power Down Mode to Active Mode
From Sleep Mode to Active Mode
5pF load on output bits (see timing diagram)
See timing diagram
V
V
V
V
Post-driver supply voltage equal to pre-driver
supply voltage V
Post-driver supply voltage above 2.25V
OVDD
OVDD
OVDD
OVDD
≥ 3.0V
= 1.7V – 3.0V
≥ 3.0V
= 1.7V – 3.0V
OVDD
= V
VDVDD
(1)
DD
0.8
-0.1
CMOS, LVDS, LVPECL, Sine Wave
Min
400
1.6
0.3
•
-10
-10
20
3
1
+
2
0
0
V
V
OVDD
OVDD
Typ
<0.5
0.8
12
10
1
3
2
www.cadeka.com
V
0.2
OVDD
Max
900
10
20
0.8
•
0.1
80
6
10
10
5
V
OVDD
-0.3
clk cycles
clk cycles
clk cycles
clk cycles
Units
% high
mV
μA
μA
ns
ps
ns
ns
pF
pF
pF
pF
V
V
V
V
V
V
V
V
pp
pp
10