ADT7467 Analog Devices, Inc., ADT7467 Datasheet - Page 32

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ADT7467

Manufacturer Part Number
ADT7467
Description
Dbcool Remote Thermal Monitor And Fan Controller
Manufacturer
Analog Devices, Inc.
Datasheet

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ADT7467
Configuration Register 4 (Reg. 0x7D)
<3:2> AINL, input threshold for 2-wire fan speed
measurements
FAN SPIN-UP
The ADT7467 has a unique fan spin-up function. It spins the
fan at 100% PWM duty cycle until two TACH pulses are de-
tected on the TACH input. Then, the PWM duty cycle goes to
the expected running value, for example, 33%. The advantage is
that fans have different spin-up characteristics and take
different times to overcome inertia. The ADT7467 runs the fans
just fast enough to overcome inertia and is quieter during spin-
up than other fans programmed to spin up for a given spin-up
time.
Fan Start-Up Timeout
To prevent the generation of false interrupts as a fan spins up
(because it is below running speed), the ADT7467 includes a
fan start-up timeout function. During this time, the ADT7467
looks for two TACH pulses. If two TACH pulses are not detected,
an interrupt is generated. Using Configuration Register 4 (0x40)
Bit 5 (FSPDIS), the functionality of this bit can be changed (see
the Disabling Fan Start-Up Timeout section).
PWM1 Configuration (Reg. 0x5C)
<2:0> SPIN, start-up timeout for PWM1
PWM2 Configuration (Reg. 0x5D)
<2:0> SPIN, start-up timeout for PWM2
00 = ±20 mV
01 = ±40 mV
10 = ±80 mV
11 = ±130 mV
000 = no start-up timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
000 = no start-up timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
Rev. A | Page 32 of 80
PWM3 Configuration (Reg. 0x5E)
<2:0> SPIN, start-up timeout for PWM3
Disabling Fan Start-Up Timeout
Although fan start-up makes fan spin-ups more quite than
fixed-time spin-ups, users can use fixed spin-up times. Setting
Bit 5 (FSPDIS) to 1 in Configuration Register 1 (Reg. 0x40)
disables the spin-up for two TACH pulses, and the fan spins up
for the fixed time selected in Reg. 0x5C to Reg. 0x5E.
PWM LOGIC STATE
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or programmed low for 100% duty cycle
(inverted).
PWM1 Configuration (Reg. 0x5C)
<4> INV
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
PWM2 Configuration (Reg. 0x5D)
<4> INV
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
PWM3 Configuration (Reg. 0x5E)
<4> INV
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Reg. 0x5F to Reg. 0x61 configure the PWM frequency for
PWM1 to PWM3, respectively. In high frequency mode, the
PWM drive frequency is 22.5 kHz and cannot be changed.
101 = 1 sec
110 = 2 sec
111 = 4 sec
000 = no start-up timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec

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