PIC16F883 Microchip Technology Inc., PIC16F883 Datasheet - Page 36
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PIC16F883
Manufacturer Part Number
PIC16F883
Description
28/40/44-pin Flash-based, 8-bit Cmos Microcontrollers With Nanowatt Technology
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F883.pdf
(288 pages)
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PIC16F882/883/884/886/887
2.2.2.6
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
REGISTER 2-6:
DS41291D-page 34
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
PIR1 Register
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = The MSSP interrupt condition has occurred, and must be cleared in software before returning from the
0 = No MSSP interrupt condition has occurred
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
Compare mode:
PWM mode:
Unused in this mode
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
R/W-0
ADIF
Interrupt Service Routine. The conditions that will set this bit are:
SPI
I
I
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
2
2
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
C Slave/Master
C Master
A transmission/reception has taken place
A transmission/reception has taken place
The initiated Start condition was completed by the MSSP module
The initiated Stop condition was completed by the MSSP module
The initiated restart condition was completed by the MSSP module
The initiated Acknowledge condition was completed by the MSSP module
A Start condition occurred while the MSSP module was idle (Multi-master system)
A Stop condition occurred while the MSSP module was idle (Multi-master system)
W = Writable bit
‘1’ = Bit is set
RCIF
R-0
TXIF
R-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
SSPIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
CCP1IF
R/W-0
software
© 2007 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
should
ensure
TMR1IF
R/W-0
bit 0
the