XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 63

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DS529-4 (v1.5) July 10, 2007
Introduction
This section describes how the various pins on a
Spartan™-3A FPGA connect within the supported
component packages, and provides device-specific thermal
characteristics. For general information on the pin functions
and the package characteristics, see the Packaging section
of UG331: Spartan-3 Generation FPGA User Guide.
•
Spartan-3A FPGAs are available in both standard and
Pb-free, RoHS versions of each package, with the Pb-free
version adding a “G” to the middle of the package code.
Table 56: Types of Pins on Spartan-3A FPGAs
DS529-4 (v1.5) July 10, 2007
Product Specification
Type / Color
CONFIG
UG331: Spartan-3 Generation FPGA User Guide
http://www.xilinx.com/bvdocs/userguides/ug331.pdf
INPUT
MGMT
VREF
Code
DUAL
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PWR
CLK
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form
differential I/Os.
Unrestricted, general-purpose input-only pin. This pin does not have an output structure
or PCI clamp diode.
Dual-purpose pin used in some configuration modes during the configuration process and
then usually available as a user I/O after configuration. If the pin is not used during
configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation
Configuration User Guide for additional information on these signals.
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other
VREF pins in the same bank, provides a reference voltage input for certain I/O standards.
If used for a reference voltage within a bank, all VREF pins within the bank must be
connected.
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16
global clock inputs that optionally clock the entire device. The exceptions are the TQ144
and the XC3S50A in the FT256 package). The RHCLK inputs optionally clock the right half
of the device. The LHCLK inputs optionally clock the left half of the device. See the Using
Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every
package has two dedicated configuration pins. These pins are powered by VCCAUX. See
the UG332: Spartan-3 Generation Configuration User Guide for additional information on
the DONE and PROG_B signals.
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated
pin. AWAKE is a Dual-Purpose pin. Unless Suspend mode is enabled in the application,
AWAKE is available as a user-I/O pin.
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
Description
<BL
Blue
>
www.xilinx.com
0
Except for the thermal characteristics, all information for the
standard package applies equally to the Pb-free package.
Pin Types
Most pins on a Spartan-3A FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3A FPGA packages, as
outlined in
follow, the individual pins are color-coded according to pin
type as in the table.
Table
Spartan-3A FPGA Family:
56. In the package footprint drawings that
Pinout Descriptions
IO_#
IO_Lxxy_#
IP_#
IP_Lxxy_#
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
IP/VREF_#
IP_Lxxy_#/VREF_#
IO/VREF_#
IO_Lxxy_#/VREF_#
IO_Lxxy_#/GCLK[15:0],
IO_Lxxy_#/LHCLK[7:0],
IO_Lxxy_#/RHCLK[7:0]
DONE, PROG_B
SUSPEND, AWAKE
Product Specification
Pin Name(s) in Type
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