XC3S100E Xilinx Corp., XC3S100E Datasheet
XC3S100E
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XC3S100E Summary of contents
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R DS312 May 29, 2007 Module 1: Introduction and Ordering Information DS312-1 (v3.4) November 9, 2006 • Introduction • Features • Architectural Overview • Package Marking • Ordering Information Module 2: Functional Description DS312-2 (v3.6) May 29, 2007 • Input/Output ...
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Complete Data Sheet 2 www.xilinx.com R DS312 May 29, 2007 Product Specification ...
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... Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling - 622+ Mb/s data transfer rate per I/O Table 1: Summary of Spartan-3E FPGA Attributes Equivalent System Logic Device Gates Cells Rows Columns XC3S100E 100K 2,160 22 XC3S250E 250K 5,508 34 XC3S500E 500K 10,476 46 XC3S1200E 1200K 19,512 60 ...
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... Notes: 1. The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom. 4 • Digital Clock Manager (DCM) Blocks provide ...
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... Slave Parallel, typically downloaded from a processor • Boundary Scan (JTAG), typically downloaded from a processor or system tester. Table 2: Available User I/Os and Differential (Diff) I/O Pairs VQ100 CP132 VQG100 CPG132 Device User Diff User XC3S100E (7) (2) (11 XC3S250E (7) (2) (7) 92 XC3S500E - - (7) XC3S1200E ...
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Introduction and Ordering Information Package Marking Figure 2 provides a top marking example for Spartan-3E FPGAs in the quad-flat packages. marking for Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the BGA ...
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... Speed Grade Package Type Pb-Free Packaging Example: XC3S250E -4 FT Device Type Speed Grade Package Type Device Speed Grade XC3S100E –4 Standard Performance XC3S250E –5 High Performance XC3S500E XC3S1200E XC3S1600E Notes: 1. The –5 speed grade is exclusively available in the Commercial temperature range. Production Stepping The Spartan-3E FPGA family uses production stepping to indicate improved capabilities or enhanced features ...
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... Added differential HSTL and SSTL I/O standards. Updated input-only pins. Added diagrams. 03/22/06 3.0 Upgraded data sheet status to Preliminary. Added XC3S100E in CP132 package and updated I/O counts for the XC3S1600E in FG320 package about dual markings for –5C and –4I product combinations to 11/09/06 3.4 Added 66 MHz PCI support and links to the Xilinx PCI LogiCORE data sheet. Indicated that Stepping 1 parts are Production status ...
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... SRL16 Shift Registers - Carry and Arithmetic Logic ♦ I/O Resources ♦ Embedded Multiplier Blocks ♦ Programmable Interconnect ♦ ISE Design Tools ♦ IP Cores ♦ Embedded Processing and Control Solutions ♦ Pin Types and Package Overview ♦ Package Drawings ♦ Powering FPGAs ♦ ...
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Functional Description Introduction As described in Architectural Overview, the Spartan™-3E FPGA architecture consists of five fundamental functional elements: • Input/Output Blocks (IOBs) • Configurable Logic Block (CLB) and Slice Resources • Block RAM • Dedicated Multipliers • Digital Clock Managers ...
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TCE OTCLK1 CK OCE OTCLK2 CK I IQ1 D IDDRIN1 IDDRIN2 CE ICLK1 CK ICE IQ2 D CE ICLK2 CK SR REV Notes: 1. ...
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... The default value is chosen automatically by the Xilinx soft- ware tools as the value depends on device size and the spe- cific device edge where the flip-flop resides. The value set by the Xilinx ISE software and the resulting effects on input ...
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R Storage Element Functions There are three pairs of storage elements in each IOB, one pair for each of the three paths possible to configure each of these storage elements as an edge-triggered D-type flip-flop (FD ...
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Functional Description Table 5: Storage Element Options (Continued) Option Switch SRHIGH/SRLOW Determines whether SR acts as a Set, which forces the storage element to a logic "1" (SRHIGH Reset, which forces a logic "0" (SRLOW) INIT1/INIT0 When Global ...
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R Register Cascade Feature In the Spartan-3E family, one of the IOBs in a differential pair can cascade its input storage elements with those in the other IOB as part of a differential pair. This is intended to make DDR ...
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Functional Description D D1 From Fabric D2 D OCLK1 OCLK2 OCLK1 OCLK2 d D1 d+2 d+4 D2 d+1 d+3 d+5 PAD d d+1 d+2 d+3 d+4 Figure 10: Output DDR Table 6: Single-Ended IOSTANDARD Bank Compatibility Single-Ended IOSTANDARD 1.2V LVTTL ...
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R Table 6: Single-Ended IOSTANDARD Bank Compatibility (Continued) Single-Ended IOSTANDARD 1.2V HSTL_III_18 - SSTL18_I - SSTL2_I - Notes: 1. N/R - Not required for input operation. Table 7: Differential IOSTANDARD Bank Compatibility Differential IOSTANDARD 1.8V LVDS_25 Input RSDS_25 Input MINI_LVDS_25 ...
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Functional Description Differential pairs can be shown in the Pin and Area Con- straints Editor (PACE) with the “Show Differential Pairs” option. A unique L-number, part of the pin name, identifies the line-pairs associated with each bank (see Descriptions in ...
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R Table 8: Programmable Output Drive Current Output Drive Current (mA IOSTANDARD LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 - - High output current drive strength and FAST output slew rates generally result in fastest I/O performance. However, ...
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Functional Description These differences are outlined for each package, such as pins that are unconnected on one device but connected on another in the same package or pins that are dedicated inputs on one package but full I/O on another. ...
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R are pulled down (PULLDOWN). The designer can control how the unused I/Os are terminated after GTS is released by setting the Bitstream Generator (BitGen) option Unused- Pin to PULLUP, PULLDOWN, or FLOAT. One clock cycle later (default), the Global ...
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... Look-Up Tables (LUTs) to imple- ment logic and two dedicated storage elements that can be used as flip-flops or latches. The LUTs can be used as a Spartan-3E FPGA Table 9: Spartan-3E CLB Resources CLB CLB Device Rows Columns XC3S100E 22 16 XC3S250E 34 26 XC3S500E 46 34 XC3S1200E 60 ...
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R . Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can depending on the slice. The upper SLICEL ...
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Functional Description Switch Matrix SHIFTOUT Slice Location Designations The Xilinx development software designates the location of a slice according to its X and Y coordinates, starting in the bottom left corner, as shown in Figure lowed by a number identifies ...
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R The SLICEM pair supports two additional functions: • Two 16x1 distributed RAM blocks, RAM16 • Two 16-bit shift registers, SRL16 Each of these elements is described in more detail in the fol- lowing sections. Logic Cells The combination of ...
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Functional Description Table 10: Slice Inputs and Outputs (Continued) Name Location CLK SLICEL/M Common SHIFTIN SLICEM Top SHIFTOUT SLICEM Bottom CIN SLICEL/M Bottom COUT SLICEL/M Top X SLICEL/M Bottom Y SLICEL/M Top XB SLICEL/M Bottom YB SLICEL/M Top XQ SLICEL/M ...
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R ing LUTs or by using the wide function multiplexers that are described later. The output of the LUT can connect to the wide multiplexer logic, the carry and arithmetic logic, or directly to a CLB out- put or to ...
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Functional Description Figure 20: Muxes and Dedicated Feedback in Spartan-3E CLB Table 11: Mux Capabilities Mux Usage F5MUX F5MUX FiMUX F6MUX F7MUX F8MUX 28 FXINB F8 FXINA F5 FXINB F6 FXINA F5 FXINB FX F7 FXINA F5 F5 FXINB F6 ...
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... R The wide multiplexers can be used by the automatic tools or instantiated in a design using a component such as the F5MUX. The symbol, signals, and function are described below. The description is similar for the F6MUX, F7MUX, and F8MUX. Each has versions with a general output, local output, or both. ...
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Functional Description G[4: F[4: Table 14: Carry Logic Functions Function CYINIT Initializes carry chain for a slice. Fixed selection of: • CIN carry input from the slice below • BX input CY0F Carry generation for ...
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R Table 14: Carry Logic Functions (Continued) Function CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of: • CYMUXF carry propagation (CYSELG = 1) • CY0G carry generation (CYSELG = 0) CYSELF Carry ...
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Functional Description The MULT_AND is useful for small multipliers. Larger multi- pliers can be built using the dedicated 18x18 multiplier blocks (see Dedicated Multipliers). Storage Elements The storage element, which is programmable as either a D-type flip-flop or a level-sensitive ...
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R STARTUP_SPARTAN3E primitive. See (STARTUP_SPARTAN3E). Table 17: Slice Storage Element Initialization Signal Description SR Set/Reset input. Forces the storage element into the state specified by the attribute SRHIGH or SRLOW. SRHIGH forces a logic “1” when SR is asserted. SRLOW ...
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Functional Description RAM16X1D WE D WCLK DPRA0 DPRA1 DPRA2 DPRA3 DS312-2_42_021305 Figure 27: Dual-Port RAM Component Table 18: Dual-Port RAM Function Inputs WE (mode) WCLK D 0 (read (read (read) ...
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R SRLC16 SHIFTIN SHIFT-REG 4 D A[3:0] A[3:0] MC15 (BY) WSG CE (SR) WE CLK CK SHIFTOUT or YB Figure 28: Logic Cell SRL16 Structure Each shift register provides a shift output MC15 for the last bit ...
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... Arrangement of RAM Blocks on Die The block RAMs are located together with the multipliers on the die in one or two columns depending on the size of the device. The XC3S100E has one column of block RAM. The Spartan-3E devices ranging from the XC3S250E to XC3S1600E have two columns of block RAM. ...
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R Table 22: Port Aspect Ratios DIP/DOP Total Data DI/DO Data Parity Bus Path Width Bus Width Width 1 (w bits) (w-p bits) (p bits Notes: 1. The ...
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Functional Description Parity 512x36 Figure 31: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B 38 Data Byte 3 Byte 2 ...
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R Block RAM Port Signal Definitions Caution! Representations of the dual-port primitive RAMB16_S[w ]_S[w ] and the single-port primitive A B RAMB16_S[w] with their associated signals are shown in Figure 32a and Figure 32b, respectively. These signals are defined in ...
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Functional Description Table 23: Block RAM Port Signals Port A Port B Signal Signal Signal Description Name Name Address Bus ADDRA ADDRB Data Input Bus DIA DIB Parity Data DIPA DIPB Input(s) Data Output Bus DOA DOB Parity Data DOPA ...
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R Block RAM Attribute Definitions A block RAM has a number of attributes that control its behavior as shown in Table 24. Table 24: Block RAM Attributes Function Initial Content for Data Memory, Loaded during Configuration Initial Content for Parity ...
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Functional Description Table 25: Block RAM Function Table (Continued) Input Signals GSR EN SSR WE CLK ↑ There are a number of different conditions under which data can be accessed at the DO outputs. Basic data ...
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R Data_in CLK WE DI ADDR DO 0000 EN DISABLED Figure 33: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected Setting the WRITE_MODE attribute to a value of WRITE_FIRST, data is written to the addressed memory location on an ...
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Functional Description Data_in CLK WE DI ADDR DO 0000 EN DISABLED Figure 35: Waveforms of Block RAM Data Operations with NO_CHANGE Selected Setting the WRITE_MODE attribute to a value of NO_CHANGE, puts the DO outputs in a latched state when ...
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R Dedicated Multipliers For additional information, refer to the “Using Embedded Multipliers” chapter in UG331. The Spartan-3E devices provide dedicated multiplier blocks per device. The multipliers are located together with the block RAM in one or two ...
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Functional Description MULT18X18SIO A[17:0] B[17:0] CEA CEB CEP CLK RSTA RSTB RSTP BCIN[17:0] Figure 37: MULT18X18SIO Primitive CEB CLK RSTB BCIN[17:0] CEB B[17:0] CLK RSTB 46 Cascading Multipliers The MULT18X18SIO primitive has two additional ports P[35:0] called BCIN and BCOUT ...
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... BCOUT port of the top-most block in a column example, Figure 39 shows the multiplier cas- cade capability within the XC3S100E FPGA, which has a single column of multiplier, four blocks tall. For clarity, the figure omits the register control inputs. BCOUT ...
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Functional Description Table 27 defines each port of the MULT18X18SIO primitive. Table 27: MULT18X18SIO Embedded Multiplier Primitives Description Signal Name Direction A[17:0] Input B[17:0] Input BCIN[17:0] Input P[35:0] Output BCOUT[17:0] Output CEA Input RSTA Input CEB Input RSTB Input CEP ...
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... This section provides a fundamental description of the DCM. The XC3S100E FPGA has two DCMs, one at the top and one at the bottom of the device. The XC3S250E and XC3S500E FPGAs each include four DCMs, two at the top and two at the bottom ...
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Functional Description CLKIN CLKFB RST Table 28: DLL Signals Signal Direction CLKIN Input CLKFB Input CLK0 Output CLK90 Output CLK180 Output CLK270 Output CLK2X Output CLK2X180 Output CLKDV Output Delay-Locked Loop (DLL) The most basic function of the DLL component ...
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R inside the DLL measures the phase error between CLKFB and CLKIN. This phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the appropriate number of delay steps to cancel ...
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Functional Description Table 30: Direct Clock Input Connections and Optional External Feedback to Associated DCMs Differential Pair Differential Pair N P Package Pin Number for Single-Ended Input VQ100 P91 P90 CP132 B7 A7 TQ144 P131 P130 P129 PQ208 P186 P185 ...
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R Table 31: Direct Clock Input and Optional External Feedback to Left-Edge DCMs (XC3S1200E and XC3S1600E) Single-Ended Pin Number by Package Type Diff. Clock VQ100 CP132 TQ144 P14 N P10 F2 P15 P P11 F1 P16 N ...
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Functional Description Every FPGA input provides a possible DCM clock input, but the path is not temperature and voltage compensated like the GCLKs. Alternatively, clock signals within the FPGA optionally provide a DCM clock input via a Global Clock Multiplexer ...
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R Accommodating Input Frequencies Beyond Spec- ified Maximums If the CLKIN input frequency exceeds the maximum permit- ted, divide it down to an acceptable value using the CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to “TRUE”, the CLKIN frequency is ...
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Functional Description The CLKFX_DIVIDE is an integer ranging from 1 to 32, inclusive and forms the denominator in example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the frequency of the output clock signal is 5/3 that of the input ...
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R FIXED Phase Shift Mode The FIXED phase shift mode shifts the DCM outputs by a fixed amount (T ), controlled by the user-specified PS PHASE_SHIFT attribute. The PHASE_SHIFT value (shown Figure 44) must be an integer ...
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Functional Description VARIABLE Phase Shift Mode In VARIABLE phase shift mode, the FPGA application dynamically adjusts the fine phase shift value using three Table 36: Signals for Variable Phase Mode Signal Direction (1) PSEN Input (1) PSCLK Input (1) PSINCDEC ...
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R example, CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST is tied to GND. Table 37: Status Logic Signals Signal Direction RST Input STATUS[7:0] Output LOCKED Output Table 38: DCM Status Bus Bit Name 0 Reserved - 1 CLKIN Stopped When ...
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Functional Description Stabilizing DCM Clocks Before User Mode The STARTUP_WAIT attribute shown in delays the end of the FPGA’s configuration process until after the DCM locks to its incoming clock frequency. This option ensures that the FPGA remains in the ...
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... Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die. 3. See Figure 47a, which shows how the eight clock lines are multiplexed on the left-hand side of the device ...
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Functional Description By contrast, the clock switch matrixes on the top and bottom edges receive signals from any of the five following sources: two GCLK pins, two DCM outputs, or one Dou- ble-Line interconnect. Table 41 indicates permissible connections between ...
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R CLK Switch LHCLK or RHCLK input Double Line DCM output* *(XC3S1200E and XC3S1600E only) Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity Quadrant Clock Routing The clock routing within the FPGA is quadrant-based, as shown in Figure 45. ...
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Functional Description BUFGMUX Output X1Y10 (Global) X0Y9 (Left Half) X1Y11 (Global) X0Y8 (Left Half) X2Y10 (Global) X0Y7 (Left Half) X2Y11 (Global) X0Y6 (Left Half) X1Y0 (Global) X0Y5 (Left Half) X1Y1 (Global) X0Y4 (Left Half) X2Y0 (Global) X0Y3 (Left Half) X2Y1 ...
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R Interconnect For additional information, refer to the “Using Interconnect“ chapter in UG331. Interconnect is the programmable network of signal path- ways between the inputs and outputs of functional elements within the FPGA, such as IOBs, CLBs, DCMs, and block ...
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Functional Description Switch IOB Matrix Switch IOB Matrix Switch IOB Matrix Switch IOB Matrix Switch IOB Matrix Figure 49: Array of Interconnect Tiles in Spartan-3E FPGA Horizontal and Vertical Long Lines (horizontal channel shown as an example) CLB Horizontal and ...
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R Direct Connections Figure 50: Interconnect Types between Two Adjacent Interconnect Tiles (Continued) The four types of general-purpose interconnect available in each channel, shown in Figure 50, are described below. Long Lines Each set of 24 long line signals spans ...
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Functional Description Configuration For additional information on configuration, refer to UG332: Spartan-3 Generation Configuration User Guide. Differences from Spartan-3 FPGAs In general, Spartan-3E FPGA configuration modes are a superset to those available in Spartan-3 FPGAs. Two new modes added in ...
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... The configuration file size for a multiple-FPGA daisy-chain design roughly equals the sum of the individual file sizes. Table 44: Number of Bits to Program a Spartan-3E FPGA (Uncompressed Bitstreams) Spartan-3E FPGA Configuration Bits XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Pin Behavior During Configuration or additional information, refer to the “Configuration Pins and Behavior during Configuration” ...
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Functional Description Table 45: Pin Behavior during Configuration (Continued) Pin Name Master Serial INIT_B INIT_B CSO_B DOUT/BUSY DOUT MOSI/CSI_B D0/DIN DIN RDWR_B A23 A22 A21 A20 A19/VS2 A18/VS1 A17/VS0 A16 A15 A14 A13 ...
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R Table 46: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V) Pin(s) I/O Standard All, including CCLK LVCMOS25 The HSWAP pin itself has an pull-up resistor enabled during configuration. However, the VCCO_0 supply voltage must be applied before the ...
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Functional Description Table 48: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0] I/O Pull-up Resistors HSWAP Value during Configuration 0 Enabled 1 Disabled The Configuration section provides detailed schematics for each configuration mode. The schematics indicate the required logic ...
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R Master Serial Mode For additional information, refer to the “Master Serial Mode” chapter in UG332. In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E FPGA configures itself from an attached Xilinx Platform P HSWAP Serial Master Mode ‘0’ M2 ...
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Functional Description Table 49: Serial Master Mode Connections Pin Name FPGA Direction HSWAP Input User I/O Pull-Up Control. When Low during configuration, enables pull-up P resistors in all I/O pins to respective I/O bank V 0: Pull-ups during configuration 1: ...
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... FPGA file sizes. Table 50: Number of Bits to Program a Spartan-3E FPGA and Smallest Platform Flash PROM Number of Spartan-3E Configuration FPGA Bits XC3S100E 581,344 XC3S250E 1,353,728 XC3S500E 2,270,208 XC3S1200E 3,841,184 5,969,696 XC3S1600E DS312-2 (v3.6) May 29, 2007 ...
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Functional Description +1.2V VCCINT P HSWAP VCCO_0 VCCO_2 DIN Serial Master Mode CCLK ‘0’ M2 DOUT ‘0’ M1 INIT_B ‘0’ M0 Spartan-3E FPGA +2.5V JTAG VCCAUX TDI TDI TDO TMS TMS TCK TCK TDO PROG_B DONE GND PROG_B Recommend open-drain ...
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R SPI Mode Variant Select S +2.5V JTAG TDI TMS TCK TDO PROG_B Recommend open-drain driver Figure 53: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B) Commands S Although SPI is a standard four-wire interface, various ...
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Functional Description P HSWAP SPI Mode ‘0’ M2 ‘0’ M1 ‘1’ M0 Variant Select Spartan-3E ‘1’ VS2 ‘1’ VS1 ‘0’ VS0 +2.5V JTAG TDI TDI TMS TMS TCK TCK TDO PROG_B PROG_B Recommend open-drain driver Figure 54: Atmel SPI-based DataFlash ...
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R Table 52: Variant Select Codes for Various SPI Serial Flash PROMs SPI Read VS2 VS1 VS0 Command FAST READ (0x0B (see Figure 53) READ (0x03 (see Figure 53) READ ARRAY (0xE8 ...
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Functional Description Table 53: Example SPI Flash PROM Connections and Pin Naming SPI Flash Pin FPGA Connection DATA_IN MOSI DATA_OUT DIN SELECT CSO_B CLOCK CCLK Not required for FPGA configuration. Must be WR_PROTECT High to program SPI Flash. Optional connection ...
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R Table 54: Serial Peripheral Interface (SPI) Connections FPGA Pin Name Direction Input User I/O Pull-Up Control. When Low HSWAP during configuration, enables pull-up P resistors in all I/O pins to respective I/O bank V CCO 0: Pull-ups during configuration ...
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Functional Description Table 54: Serial Peripheral Interface (SPI) Connections (Continued) FPGA Pin Name Direction Open-drain Initialization Indicator. Active Low. INIT_B bidirectional Goes Low at start of configuration during I/O Initialization memory clearing process. Released at end of memory clearing, when ...
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... RISC processor core integrated in the Spartan-3E FPGA. See Using the SPI Flash Interface after Table 56: Number of Bits to Program a Spartan-3E , POR FPGA and Smallest SPI Flash PROM Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Figure 54. Release the CCLK Frequency In SPI Flash mode, the FPGA’s internal oscillator generates the configuration clock frequency. The FPGA provides this clock on its CCLK output pin, driving the PROM’ ...
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Functional Description ConfigRate = 12 or lower. SPI Flash PROMs that support the FAST READ command support higher data rates. Some such PROMs support up to ConfigRate = 25 and beyond but require careful data sheet analysis. See eral Interface ...
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R Daisy-Chaining DESIGN NOTE: SPI mode daisy chains are supported only in ! Stepping 1 and later silicon versions. If the application requires multiple FPGAs with different con- figurations, then configure the FPGAs using a daisy chain, as shown in ...
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... The FPGA generates 24-bit address lines to access an attached parallel Flash. Only 20 address lines are generated for Spartan-3E FPGAs in the TQ144 package. Similarly, the XC3S100E FPGA in the CP132 package only has 20 address lines while the XC3S250E and XC3S500E FPGAs in the same package have 24 address lines ...
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R Not available in VQ100 package BPI Mode +2.5V JTAG TDI TMS TCK TDO PROG_B Recommend open-drain driver Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs A During configuration, the value of the M0 mode ...
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Functional Description This addressing flexibility allows the FPGA to share the par- allel Flash PROM with an external or embedded processor. Depending on the specific processor architecture, the pro- cessor boots either from the top or bottom of memory. The ...
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R Table 58: Byte-Wide Peripheral Interface (BPI) Connections (Continued) Pin Name FPGA Direction HDC Output PROM Write Enable LDC2 Output PROM Byte Mode D A[23:0] Output Address D[7:0] Input Data Input CSO_B Output Chip Select Output. Active Low. BUSY Output ...
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Functional Description Table 58: Byte-Wide Peripheral Interface (BPI) Connections (Continued) Pin Name FPGA Direction INIT_B Open-drain Initialization Indicator. Active bidirectional I/O Low. Goes Low at start of configuration during the Initialization memory clearing process. Released at the end of memory ...
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... R Table 59: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM Uncompressed Spartan-3E FPGA File Sizes (bits) XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Compatible Flash Families The Spartan-3E BPI configuration interface operates with a wide variety x8/x16 parallel NOR Flash devices. Table 60 provides a few Flash memory families that operate with the Spartan-3E BPI interface ...
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Functional Description The address, data, and LDC1 (OE#) and HDC (WE#) con- trol signals are common to all parallel peripherals. Connect the chip-select input on each additional peripheral to one of the FPGA user I/O pins. If HSWAP = 0 ...
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R Some x8/x16 Flash PROMs have a long setup time require- ment on the BYTE# signal. For the FPGA to configure cor- rectly, the PROM must mode with BYTE power-on or when the FPGA’s ...
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... FPGA-based programmer is downloaded into the FPGA via JTAG. Then the FPGA performs the Flash PROM pro- gramming algorithms and receives programming data from the host via the FPGA’s JTAG interface. See Chapter 11 in Embedded System Tools Reference 94 V VCCO_0 VCCO_0 ...
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R memory locations. After the FPGA completes configuration, the application initially loaded into the FPGA performs a board-level or system test using FPGA logic. If the test is successful, the FPGA then triggers a MultiBoot event, caus- ing the FPGA ...
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Functional Description Intelligent Download Host VCC Configuration Memory Source READ/WRITE - Internal memory - Disk drive - Over network - Over RF link GND - Microcontroller - Processor - Tester - Computer PROG_B Recommend open-drain driver Slave Parallel Mode For ...
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R After configuration, all of the interface pins except DONE and PROG_B are available as user I/Os. Alternatively, the bidirectional SelectMAP configuration interface is available after configuration. To continue using SelectMAP mode, set the Persist bitstream generator option to Yes. ...
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Functional Description Table 64: Slave Parallel Mode Connections (Continued) Pin Name FPGA Direction INIT_B Open-drain Initialization Indicator. Active Low. bidirectional I/O Goes Low at the start of configuration during the Initialization memory clearing process. Released at the end of memory ...
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R Parallel V Intelligent Download Host VCC DATA[7:0] Configuration BUSY Memory Source SELECT READ/WRITE • Internal memory CLOCK • Disk drive • PROG_B Over network • DONE Over RF link INIT_B GND • Microcontroller • Processor • Tester PROG_B Recommend ...
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Functional Description V Intelligent Download Host VCC Configuration CLOCK Memory Source SERIAL_OUT PROG_B • Internal memory DONE • Disk drive INIT_B • Over network • Over RF link GND • Microcontroller • Processor • Tester • Computer PROG_B Recommend open-drain ...
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R Table 65: Slave Serial Mode Connections Pin Name FPGA Direction HSWAP Input User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank 0: Pull-up during configuration 1: No pull-ups M[2:0] ...
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Functional Description Intelligent V Download Host VCC Configuration CLOCK Memory Source SERIAL_OUT PROG_B • Internal memory DONE • Disk drive • INIT_B Over network • Over RF link GND • Microcontroller • Processor • Tester • Computer PROG_B Recommend open-drain ...
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... CMOS output powered from +2.5V. The TDO output can directly drive a 3.3V input but with reduced noise immunity. See XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for additional information. Table 66: Spartan-3E JTAG Device Identifiers 4-Bit Revision Code Spartan-3E FPGA Step 0 Step 1 XC3S100E 0x0 0x1 XC3S250E 0x0 0x1 0x0 XC3S500E 0x4 0x2 ...
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Functional Description Maximum Bitstream Size for Daisy-Chains The maximum bitstream length supported by Spartan-3E FPGAs in serial daisy-chains is 4,294,967,264 bits (4 Gbits), roughly equivalent to a daisy-chain with 720 XC3S1600E FPGAs. This is a limit only for serial daisy-chains ...
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Option = Bitstream Generator (BitGen) Option Option = Design Attribute Power On Reset (POR) VCCO_2 V CCO2T POWER_GOOD VCCINT V CCINTT VCCAUX V CCAUXT PROG_B Glitch Filter CCLK 1 1 TCK 0 ConfigRate 0 Internal M1 Oscillator M2 LOCKED DCM ...
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Functional Description 106 Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 2 > 1V CCO Yes Yes Clear configuration PROG_B = Low memory No INIT_ B = High? Yes M[2:0] ...
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R Load JPROG instruction Figure 68: Boundary-Scan Configuration Flow Diagram DS312-2 (v3.6) May 29, 2007 Product Specification Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 2 > 1V CCO Yes ...
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Functional Description Start-Up At the end of configuration, the FPGA automatically pulses the Global Set/Reset (GSR) signal, placing all flip-flops in a known state. After configuration completes, the FPGA switches over to the user application loaded into the FPGA. The ...
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... Table 67: Readback Support in Spartan-3E FPGAs Temperature Range Block RAM Readback General Readback (registers, distributed RAM) library primi- Table 67. The Read- www.xilinx.com Functional Description Commercial Speed Grade -4 -5 All Spartan-3E No Yes FPGAs XC3S100E Yes Yes XC3S250E Yes Yes XC3S500E Yes Yes XC3S1200E No Yes XC3S1600E No Yes Industrial -4 ...
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Functional Description Bitstream Generator (BitGen) Options For additional information, refer to the “Configuration Bit- stream Generator (BitGen) Settings” chapter in UG332. Various Spartan-3E FPGA functions are controlled by spe- cific bits in the configuration bitstream image. These values Table 68: ...
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R Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued) Pins/Function Values Option Name Affected (default) LCK_cycle DCMs, NoWait Configuration Startup DonePin DONE pin Pullup Pullnone DriveDone DONE pin DonePipe DONE pin ProgPin ...
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Functional Description Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued) Pins/Function Values Option Name Affected (default) Security JTAG, SelectMAP, Readback, Level1 Partial reconfiguration Level2 CRC Configuration Enable Disable Persist SelectMAP interface pins, BPI mode, Slave mode, Configuration Powering Spartan-3E ...
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... Spartan-3 and Spartan-3E FPGAs. The Xilinx Power Corner vides links to vendor solution guides and Xilinx power esti- mation and analysis tools. Power Distribution System (PDS) Design and Decoupling/Bypass Capacitors Good power distribution system (PDS) design is important for all FPGA designs, but especially so for high perfor- mance applications, greater than 100 MHz ...
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... MHz (200 MHz for XC3S1200E) Split ranges at 5 – 90 MHz and 220 – 307 MHz (single range 5 – 307 MHz for XC3S1200E) No, single FPGA only (1) No Yes: XC3S100E, XC3S250E, XC3S500E ( XC3S1200E, XC3S1600E Requires V before V CCINT mark. See for additional information. ...
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R Software Version Requirements Production Spartan-3E applications must be processed using the Xilinx ISE 8.1i, Service Pack 3 or later develop- ment software, using the v1.21 or later speed files. The ISE 8.1i software implements critical bitstream generator updates. DS312-2 ...
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Functional Description Revision History The following table shows the revision history for this document. Date Version 03/01/05 1.0 Initial Xilinx release. 03/21/05 1.1 Updated 11/23/05 2.0 Updated values of configuration bitstream sizes for XC3S250E through XC3S1600E in and Limitations when ...
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R Date Version 11/09/06 3.4 Updated the description of the is no longer supported. Updated Replaced missing text in Updated parallel NOR Flash devices in was added beginning with ISE 8.1i iMPACT software for STMicro and Atmel SPI PROMs. Updated ...
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Functional Description 118 www.xilinx.com R DS312-2 (v3.6) May 29, 2007 Product Specification ...
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R DS312-3 (v3.6) May 29, 2007 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...
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DC and Switching Characteristics Power Supply Specifications Table 73: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes ...
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R General Recommended Operating Conditions Table 76: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX (2,3,4) V Input voltage extremes to avoid ...
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DC and Switching Characteristics General DC Characteristics for I/O Pins Table 77: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins (2) I Current through ...
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... R Quiescent Current Requirements Table 78: Quiescent Supply Current Characteristics Symbol Description I Quiescent V supply current XC3S100E CCINTQ CCINT I Quiescent V supply current CCOQ CCO I Quiescent V supply CCAUXQ CCAUX current Notes: 1. The numbers in this table are based on the conditions set forth in 2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled ...
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DC and Switching Characteristics Single-Ended I/O Standards Table 79: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers CCO IOSTANDARD Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 (4) LVCMOS18 1.65 (4) ...
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R Table 80: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOSTANDARD Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – ...
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DC and Switching Characteristics Differential I/O Standards Internal Logic V V GND level Table 81: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) LVDS_25 2.375 BLVDS_25 2.375 MINI_LVDS_25 2.375 (2) LVPECL_25 RSDS_25 ...
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R Internal Logic V OUTN V OUTP GND level Table 82: DC Characteristics of User I/Os Using Differential Signal Standards V OD IOSTANDARD Min Typ Attribute (mV) (mV) LVDS_25 250 350 BLVDS_25 250 350 MINI_LVDS_25 300 – RSDS_25 100 – ...
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... Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. Table 83: Spartan-3E v1.26 Speed Grade Designations Device Advance XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Table 84 provides the history of the Spartan-3E speed files since all devices reached Production status ...
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... XC3S100E output drive, Fast slew XC3S250E (3) rate, with DCM XC3S500E XC3S1200E XC3S1600E (2) LVCMOS25 , 12mA XC3S100E output drive, Fast slew XC3S250E rate, without DCM XC3S500E XC3S1200E XC3S1600E Table 94 and are based on the operating conditions set forth in www.xilinx.com DC and Switching Characteristics Speed Grade ...
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... XC3S500E 3 XC3S1200E 3 XC3S1600E (3) LVCMOS25 , 0 XC3S100E IFD_DELAY_VALUE = 0, XC3S250E (4) with DCM XC3S500E XC3S1200E XC3S1600E (3) LVCMOS25 , 2 XC3S100E IFD_DELAY_VALUE = 3 XC3S250E default software setting 3 XC3S500E 3 XC3S1200E 3 XC3S1600E Table 94 and are based on the operating conditions set forth in Table Table www.xilinx.com Speed Grade -5 -4 Device Min Min 2.65 2 ...
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... DC and Switching Characteristics Speed Grade -5 IFD_ DELAY_ Device Min VALUE= 0 All 1.84 2 XC3S100E 6.12 3 All Others 6.76 0 All –0.76 –0.76 2 XC3S100E –3.74 –3.74 3 All Others –4.32 –4.32 All 1.00 and are based on the operating conditions set forth in Max -4 Min Units 2.12 ns 7. 1.15 ns Units ...
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... These adjustments are used to convert input path times originally 0.15 ns specified for the LVCMOS25 standard to times that correspond to other signal standards. www.xilinx.com Speed Grade -5 IFD_ Device Max Max 0 All 1.96 2.25 2 XC3S100E 5.40 5.97 3 All Others 6.30 7.20 and are based on the operating conditions set forth in Add the Adjustment Below Speed Grade -5 0.48 0.49 0.39 0.39 0.48 ...
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R Table 91: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the IOCKP Output Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the Output pin Propagation ...
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DC and Switching Characteristics Table 92: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at IOCKHZ the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters ...
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R Table 93: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...
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DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test condi- tions. Table 94 lists the conditions to use for each standard. The method for measuring Input timing ...
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R Table 94: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V (V) REF DIFF_HSTL_I_18 0.9 DIFF_HSTL_III_18 1.1 DIFF_SSTL18_I 0.9 DIFF_SSTL2_I 1.25 Notes: 1. Descriptions of the relevant symbols are as follows: V – The reference voltage ...
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... Table 95 and Table 96 provide the essential SSO guide- lines. For each device/package combination, Table 95: Equivalent V /GND Pairs per Bank CCO Device VQ100 CP132 XC3S100E 2 XC3S250E 2 XC3S500E - XC3S1200E - XC3S1600E - 138 vides the number of equivalent V output signal standard and drive strength, ...
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R Table 96: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO Package Type Signal Standard VQ TQ (IOSTANDARD) 100 144 Single-Ended Standards LVTTL Slow ...
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DC and Switching Characteristics Configurable Logic Block (CLB) Timing Table 97: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, CKO the time from the active transition at the CLK input to data appearing at ...
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R Table 98: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data SHCKO appearing on the distributed RAM output Setup Times T Setup time of data at the BX ...
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DC and Switching Characteristics Clock Buffer/Multiplexer Switching Characteristics Table 100: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as ...
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Embedded Multiplier Timing Table 101 Embedded Multiplier Timing Symbol Combinatorial Delay T Combinatorial multiplier propagation delay from the A and B MULT inputs to the P outputs, assuming 18-bit inputs and a 36-bit ...
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DC and Switching Characteristics Block RAM Timing Table 102: Block RAM Timing Symbol Clock-to-Output Times T When reading from block RAM, the delay from the BCKO active transition at the CLK input to data appearing at the DOUT output Setup ...
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... Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock peri- ods sampled histogram of cycle-cycle jitter, the mean value is zero. Description Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E (3) XC3S1200E Stepping 1 ...
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... XC3S1600E XC3S1200E Stepping 1 All Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E XC3S1200E Stepping 1 All Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E XC3S1200E Stepping 1 All Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E XC3S1200E Stepping 1 All All All www.xilinx.com Speed Grade -5 -4 Min Max Min Max Units ...
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R Table 104: Switching Characteristics for the DLL (Continued) Symbol (4) Phase Alignment CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs CLKOUT_PHASE_DLL Phase offset between DLL outputs Lock Time (3) LOCK_DLL When using the DLL alone: The time from ...
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... Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used 148 Description F < 150 MHz CLKFX F > 150 MHz CLKFX Description Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E Stepping 0 XC3S1200E Stepping 1 All www.xilinx.com Speed Grade -5 -4 Min ...
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R Table 106: Switching Characteristics for the DFS (Continued) Symbol Lock Time (2) LOCK_FX The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 ...
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DC and Switching Characteristics Miscellaneous DCM Timing Table 109: Miscellaneous DCM Timing Symbol (1) DCM_RST_PW_MIN Minimum duration of a RST pulse width (2) DCM_RST_PW_MAX Maximum duration of a RST pulse width (3) DCM_CONFIG_LAG_TIME Maximum duration from V configuration successfully completed ...
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... V CCINT CCAUX CCO Table www.xilinx.com DC and Switching Characteristics T ICCK DS312-3_01_103105 All Speed Grades Device Min Max XC3S100E - 5 XC3S250E - 5 XC3S500E - 5 XC3S1200E - 5 XC3S1600E - 7 All 0.5 - XC3S100E - 0.5 XC3S250E - 0.5 XC3S500E - 1 XC3S1200E - 2 XC3S1600E - 2 All 250 - All 0.5 4.0 76. This means power must be applied to all V 1.2V 2.5V Units μs ms ...
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DC and Switching Characteristics Configuration Clock (CCLK) Characteristics Table 111: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T CCLK1 ConfigRate setting T CCLK3 T CCLK6 T CCLK12 T CCLK25 T CCLK50 Notes: ...
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R Master Serial and Slave Serial Mode Timing PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 75: Waveforms for Master Serial and Slave Serial Configuration Table 115: Timing for the Master Serial and Slave Serial Configuration Modes ...
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DC and Switching Characteristics Slave Parallel Mode Timing PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) High-Z BUSY (Output) Notes possible to abort configuration by pulling CSI_B Low in a given ...
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R Table 116: Timing for the Slave Parallel Configuration Mode (Continued) Symbol Hold Times T The time from the active edge of the CCLK pin to the point when data is last SMCCD held at the D0-D7 pins T The ...
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DC and Switching Characteristics Serial Peripheral Interface (SPI) Configuration Timing PROG_B (Input) HSWAP HSWAP must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) CCLK DIN ...
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R Table 118: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input hold time DH ...
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DC and Switching Characteristics Byte Peripheral Interface (BPI) Configuration Timing PROG_B (Input) HSWAP HSWAP must be stable before INIT_B goes High and remain constant throughout configuration. CSI_B (Input) RDWR_B (Input) M[2:0] <0:1:1> (Input) T MINIT INIT_B (Open-Drain) LDC[2:0] HDC CSO_B ...
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R Table 119: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode (Continued) Symbol T Address A[23:0] outputs valid after CCLK falling edge CCO T Setup time on D[7:0] data inputs before CCLK falling edge DCC T Hold time on D[7:0] ...
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DC and Switching Characteristics IEEE 1149.1/1553 JTAG Test Access Port Timing TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 122: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the ...
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... Revision Table 83. Expanded description in Note 2, and Table 87. Updated other I/O timing in Table 90 and Table 92. Added XC3S100E FPGA in CP132 package to slice flip-flop timing by 100 and SRL16 timing in Table 99. Updated global clock timing, removed left/right Table 100. Updated block RAM timing in 103, Table ...
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DC and Switching Characteristics 162 www.xilinx.com R DS312-3 (v3.6) May 29, 2007 Product Specification ...
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R DS312-4 (v3.6) May 29, 2007 Introduction This section describes the various pins on a Spartan™-3E FPGA and how they connect within the supported compo- nent packages. Table 123: Types of Pins on Spartan-3E FPGAs Type / Color Code I/O ...
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Pinout Descriptions Table 123: Types of Pins on Spartan-3E FPGAs (Continued) Type / Color Code CONFIG Dedicated configuration pin. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See the ...
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R Package Overview Table 124 shows the eight low-cost, space-saving produc- tion package styles for the Spartan-3E family. Each pack- age style is available as a standard and an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an extra ...
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Pinout Descriptions Mechanical Drawings Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in Table 126. Table 126: Xilinx Package Mechanical Drawings Package VQ100 / VQG100 http://www.xilinx.com/bvdocs/packages/vq100.pdf CP132 / CPG132 http://www.xilinx.com/bvdocs/packages/cp132.pdf TQ144 ...
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... R Table 128: Maximum User I/O by Package Maximum User I/Os and Device Package Input-Only XC3S100E 66 VQ100 XC3S250E 66 XC3S100E 83 XC3S250E CP132 92 XC3S500E 92 XC3S100E 108 TQ144 XC3S250E 108 XC3S250E 158 PQ208 XC3S500E 158 XC3S250E 172 XC3S500E FT256 190 XC3S1200E 190 XC3S500E 232 XC3S1200E FG320 250 XC3S1600E ...
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... The junction-to-case thermal resistance (θ difference between the temperature measured on the pack- Table 129: Spartan-3E Package Thermal Characteristics Junction-to-Case Package Device VQ100 XC3S100E XC3S250E CP132 XC3S100E XC3S250E XC3S500E TQ144 XC3S100E XC3S250E PQ208 XC3S250E XC3S500E FT256 XC3S250E XC3S500E XC3S1200E FG320 XC3S500E XC3S1200E XC3S1600E FG400 ...
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... R VQ100: 100-lead Very-thin Quad Flat Package The XC3S100E and the XC3S250E devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices share a common footprint for this package as shown in Table 130 and Figure 81. Table 130 lists all the package pins. They are sorted by bank number and then by pin name of the largest device ...
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... Pinout Descriptions Table 130: VQ100 Package Pinout (Continued) XC3S100E XC3S250E Bank Pin Name 3 IO_L02P_3 3 IO_L03N_3/LHCLK1 3 IO_L03P_3/LHCLK0 3 IO_L04N_3/LHCLK3 3 IO_L04P_3/LHCLK2 3 IO_L05N_3/LHCLK5 3 IO_L05P_3/LHCLK4 3 IO_L06N_3/LHCLK7 3 IO_L06P_3/LHCLK6 3 IO_L07N_3 3 IO_L07P_3 VCCO_3 3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... R User I/Os by Bank Table 131 indicates how the 66 available user-I/O pins are distributed between the four I/O banks on the VQ100 pack- age. Table 131: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package Package Maximum Edge I/O Bank I/O Top 0 15 Right 1 15 Bottom ...
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Pinout Descriptions VQ100 Footprint In Figure 81, note pin 1 indicator in top-left corner and logo orientation. PROG_B 1 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 5 VCCINT 6 GND 7 VCCO_3 8 IO_L03P_3/LHCLK0 9 IO_L03N_3/LHCLK1 10 IO_L04P_3/LHCLK2 11 IO_L04N_3/LHCLK3 ...
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... DS312-4 (v3.6) May 29, 2007 Product Specification nected to VCCINT to maintain density migration compatibil- ity. Similarly, the A4, C1, and P10 balls on the XC3S100E FPGA are not connected but should be connected to GND to maintain density migration compatibility. The XC3S100E FPGA has four fewer BPI address pins, A[19:0], whereas the XC3S250E and XC3S500E support A[23:0] ...
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... Pinout Descriptions Table 132: CP132 Package Pinout (Continued) XC3S100E Bank Pin Name 0 VCCO_0 0 VCCO_0 1 IO/A0 1 IO/VREF_1 1 IO_L01N_1/A15 1 IO_L01P_1/A16 1 IO_L02N_1/A13 1 IO_L02P_1/A14 1 IO_L03N_1/A11 1 IO_L03P_1/A12 1 IO_L04N_1/A9/RHCLK1 1 IO_L04P_1/A10/RHCLK0 1 IO_L05N_1/A7/RHCLK3/TRDY1 1 IO_L05P_1/A8/RHCLK2 1 IO_L06N_1/A5/RHCLK5 1 IO_L06P_1/A6/RHCLK4/IRDY1 1 IO_L07N_1/A3/RHCLK7 1 IO_L07P_1/A4/RHCLK6 1 IO_L08N_1/A1 1 IO_L08P_1/A2 1 IO_L09N_1/LDC0 1 IO_L09P_1/HDC ...
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... R Table 132: CP132 Package Pinout (Continued) XC3S100E Bank Pin Name 2 IO_L06P_2/D2/GCLK2 2 IO_L07N_2/DIN/D0 2 IO_L07P_2/ IO_L10N_2/VS1/A18 2 IO_L10P_2/VS2/A19 2 IO_L11N_2/CCLK 2 IO_L11P_2/VS0/A17 2 IP/VREF_2 2 IP_L05N_2/M2/GCLK1 2 IP_L05P_2/RDWR_B/GCLK0 2 VCCO_2 2 VCCO_2 IP/VREF_3 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3 3 IO_L02P_3 3 N. IO_L04N_3/LHCLK1 3 IO_L04P_3/LHCLK0 3 IO_L05N_3/LHCLK3/IRDY2 3 IO_L05P_3/LHCLK2 3 IO_L06N_3/LHCLK5 3 IO_L06P_3/LHCLK4/TRDY2 3 IO_L07N_3/LHCLK7 ...
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... Pinout Descriptions Table 132: CP132 Package Pinout (Continued) XC3S100E Bank Pin Name 3 IO_L09P_3 3 IP/VREF_3 3 VCCO_3 3 VCCO_3 GND N.C. (GND) GND GND GND N.C. (GND) GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... Table 133 shows how the 83 available user-I/O pins are dis- tributed on the XC3S100E FPGA packaged in the CP132 package. Table 134 indicates how the 92 available user-I/O Table 133: User I/Os Per Bank for the XC3S100E in the CP132 Package Package Maximum Edge I/O Bank Top ...
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... Table 135 between Spartan-3E devices available in the CP132 pack- age. The XC3S100E is duplicated on both the left and right sides of the table to show migrations to and from the XC3S250E and the XC3S500E. The arrows indicate the direction for easy migration. A double-ended arrow ( ...
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... P VCCINT VCCO_2 DOUT D5 BUSY 16 to I/O: Unrestricted, 22 general-purpose user I/O INPUT: Unrestricted general-purpose input pin CONFIG: Dedicated 2 configuration pins N.C.: Unconnected balls on 9 the XC3S100E FPGA ( ) DS312-4 (v3.6) May 29, 2007 Product Specification Bank I/O VCCAUX GND VCCO_0 L07P_0 L05N_0 GCLK10 GCLK7 I/O INPUT ...
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... Pinout Descriptions TQ144: 144-lead Thin Quad Flat Package The XC3S100E and the XC3S250E FPGAs are available in the 144-lead thin quad flat package, TQ144. Both devices share a common footprint for this package as shown in Table 136 and Figure 83. Table 136 lists all the package pins. They are sorted by bank number and then by pin name of the largest device ...
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... R Table 136: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name 1 IO_L01P_1/A16 1 IO_L02N_1/A13 1 IO_L02P_1/A14 1 IO_L03N_1/A11 1 IO_L03P_1/A12 1 IO_L04N_1/A9/RHCLK1 1 IO_L04P_1/A10/RHCLK0 1 IO_L05N_1/A7/RHCLK3/TRDY1 1 IO_L05P_1/A8/RHCLK2 1 IO_L06N_1/A5/RHCLK5 1 IO_L06P_1/A6/RHCLK4/IRDY1 1 IO_L07N_1/A3/RHCLK7 1 IO_L07P_1/A4/RHCLK6 1 IO_L08N_1/A1 1 IO_L08P_1/A2 1 IO_L09N_1/LDC0 1 IO_L09P_1/HDC 1 IO_L10N_1/LDC2 1 IO_L10P_1/LDC1 ...
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... Pinout Descriptions Table 136: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name 2 IO_L08P_2/M0 2 IO_L09N_2/VS1/A18 2 IO_L09P_2/VS2/A19 2 IO_L10N_2/CCLK 2 IO_L10P_2/VS0/A17 IP_L03N_2/VREF_2 2 IP_L03P_2 2 IP_L06N_2/M2/GCLK1 2 IP_L06P_2/RDWR_B/GCLK0 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 IP/VREF_3 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3/VREF_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 3 IO_L04N_3/LHCLK1 3 IO_L04P_3/LHCLK0 3 IO_L05N_3/LHCLK3/IRDY2 3 IO_L05P_3/LHCLK2 3 IO_L06N_3/LHCLK5 3 IO_L06P_3/LHCLK4/TRDY2 ...
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... R Table 136: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name IP/VREF_3 3 VCCO_3 3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... Pinout Descriptions User I/Os by Bank Table 137 and Table 138 indicate how the 108 available user-I/O pins are distributed between the four I/O banks on the TQ144 package. Table 137: User I/Os Per Bank for the XC3S100E in the TQ144 Package Package Maximum Edge I/O Bank Top 0 Right ...
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... R TQ144 Footprint Note pin 1 indicator in top-left corner and logo orientation. Double arrows ( ) indicates a pinout migration difference between the XC3S100E and XC3S250E. PROG_B 1 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 IO_L03P_3 7 IO_L03N_3 8 VCCINT GND 11 IP/VREF_3 12 VCCO_3 13 IO_L04P_3/LHCLK0 14 IO_L04N_3/LHCLK1 15 IO_L05P_3/LHCLK2 16 IO_L05N_3/LHCLK3 GND 19 IO_L06P_3/LHCLK4 ...
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Pinout Descriptions PQ208: 208-pin Plastic Quad Flat Package The 208-pin plastic quad flat package, PQ208, supports two different Spartan-3E FPGAs, including the XC3S250E and the XC3S500E. Table 140 lists all the PQ208 package pins. They are sorted by bank number ...
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R Table 140: PQ208 Package Pinout (Continued) XC3S250E XC3S500E Bank Pin Name 1 IO_L14N_1 1 IO_L14P_1 1 IO_L15N_1/LDC0 1 IO_L15P_1/HDC 1 IO_L16N_1/LDC2 1 IO_L16P_1/LDC1 IP/VREF_1 ...
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Pinout Descriptions Table 140: PQ208 Package Pinout (Continued) XC3S250E XC3S500E Bank Pin Name 3 IO_L10P_3/LHCLK6 3 IO_L11N_3 3 IO_L11P_3 3 IO_L12N_3 3 IO_L12P_3 3 IO_L13N_3 3 IO_L13P_3 3 IO_L14N_3 3 IO_L14P_3 3 IO_L15N_3 3 IO_L15P_3 3 IO_L16N_3 3 IO_L16P_3 3 ...
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R User I/Os by Bank Table 141 indicates how the 158 available user-I/O pins are distributed between the four I/O banks on the PQ208 pack- age. Table 141: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 ...
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Pinout Descriptions PQ208 Footprint (Left) 190 PROG_B 1 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 VCCAUX 7 IO_L03P_3 8 IO_L03N_3 9 GND 10 IO_L04P_3 11 IO_L04N_3 12 VCCINT IO_L05P_3 15 IO_L05N_3 16 GND 17 ...
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R PQ208 Footprint (Right) Bank 0 Bank 2 DS312-4 (v3.6) May 29, 2007 Product Specification 156 GND 155 TMS 154 IP 153 IO_L16N_1/LDC2 152 IO_L16P_1/LDC1 151 IO_L15N_1/LDC0 150 IO_L15P_1/HDC 149 VCCAUX 148 IP 147 IO_L14N_1 146 IO_L14P_1 145 IO_L13N_1 144 ...
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Pinout Descriptions FT256: 256-ball Fine-pitch, Thin Ball Grid Array The 256-ball fine-pitch, thin ball grid array package, FT256, supports three different Spartan-3E FPGAs, including the XC3S250E, the XC3S500E, and the XC3S1200E. Table 142 lists all the package pins. They are ...
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R Table 142: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 0 IO_L12N_0 0 IO_L12P_0 IO_L14N_0/VREF_0 0 IO_L14P_0 0 IO_L15N_0 0 IO_L15P_0 0 IO_L17N_0/VREF_0 0 IO_L17P_0 0 IO_L18N_0 0 IO_L18P_0 0 ...
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Pinout Descriptions Table 142: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 1 IO_L04N_1/VREF_1 1 IO_L04P_1 IO_L06N_1 1 IO_L06P_1 1 IO_L07N_1/A11 1 IO_L07P_1/A12 1 IO_L08N_1/VREF_1 1 IO_L08P_1 1 IO_L09N_1/A9/RHCLK1 1 IO_L09P_1/A10/RHCLK0 ...
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R Table 142: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name IO/VREF_1 1 IP/VREF_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 2 ...
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Pinout Descriptions Table 142: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 2 N. IO_L09N_2/D6/GCLK13 2 IO_L09P_2/D7/GCLK12 2 IO_L10N_2/D3/GCLK15 2 IO_L10P_2/D4/GCLK14 2 IO_L12N_2/D1/GCLK3 2 IO_L12P_2/D2/GCLK2 2 IO_L13N_2/DIN/D0 2 IO_L13P_2/ ...
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R Table 142: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3/VREF_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 IO_L05N_3 3 IO_L05P_3 3 IO_L06N_3 3 IO_L06P_3 3 ...
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Pinout Descriptions Table 142: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name IO_L18N_3 3 IO_L18P_3 3 IO_L19N_3 3 IO_L19P_3 ...
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R Table 142: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Pinout Descriptions User I/Os by Bank Table 143, Table 144, and Table 145 available user-I/O pins are distributed between the four I/O banks on the FT256 package. Table 143: User I/Os Per Bank on XC3S250E in the FT256 Package Package ...