XC9500 Xilinx Corp., XC9500 Datasheet
XC9500
Related parts for XC9500
XC9500 Summary of contents
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... I/Os may be configured for 3. operation. All outputs provide 24 mA drive. XC9572 XC95108 XC95144 72 108 144 1,600 2,400 3,200 72 108 144 7.5 7.5 7.5 4.5 4.5 4.5 4.5 4.5 4.5 125 125 125 83.3 83.3 83.3 www.xilinx.com 1-800-255-7778 1, logic density of the XC9500 devices Table 2. The XC9500 fam- XC95216 XC95288 216 288 4,800 6,400 216 288 10 15 6.0 8.0 6.0 8.0 111.1 92.2 66.7 56.6 1 ...
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... BGA - Architecture Description Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully intercon- nected by the Fast CONNECT™ switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and ...
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... FB. These paths are used for creating very fast counters and state machines where all state registers are within the same FB. Macrocell 1 Product Programmable Term AND-Array Allocators Macrocell 18 1 Global Global Set/Reset Clocks Figure 2: XC9500 Function Block www.xilinx.com 1-800-255-7778 18 To Fast CONNECT II Switch Matrix 18 OUT To I/O Blocks 18 PTOE 3 DS063_02_110501 3 ...
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... XC9500 In-System Programmable CPLD Family Macrocell Each XC9500 macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions control inputs including clock, set/reset, and output enable ...
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... Figure 4: Macrocell Clock and Set/Reset Capability DS063 (v5.1) September 22, 2003 Product Specification XC9500 In-System Programmable CPLD Family term clock. Both true and complement polarities of a GCK pin can be used within the device. A GSR input is also pro- vided to allow user registers to be set to a user-defined state ...
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... XC9500 In-System Programmable CPLD Family Product Term Allocator The product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator Figure 5: Macrocell Logic Using Direct Product Term ...
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... In this example, the incremental delay is only 2 product terms are available to any macrocell, with a maxi- mum incremental delay PTA. DS063 (v5.1) September 22, 2003 Product Specification XC9500 In-System Programmable CPLD Family Product Term Allocator Figure All 90 * PTA Figure 7: Product Term Allocation Over Several www ...
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... XC9500 In-System Programmable CPLD Family The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell From Lower Macrocell 8 To Upper Macrocell Product Term Allocator To Lower Macrocell Figure 8: Product Term Allocator Logic www.xilinx.com 1-800-255-7778 Product Term Set Global Set/Reset ...
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... Wired-AND Capability DS063 (v5.1) September 22, 2003 Product Specification XC9500 In-System Programmable CPLD Family The Fast CONNECT switch matrix is capable of combining multiple internal connections into a single wired-AND output before driving the destination FB. This provides additional logic capability and increases the effective logic fan-in of the destination FB without any additional timing delay ...
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... XC9500 In-System Programmable CPLD Family I/O Block The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. See details. The input buffer is compatible with standard 5V CMOS, 5V TTL, and 3 ...
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... OUT IN CPLD 0V 3.3V 3.3V GND 0V (a) Figure 12: XC9500 Devices in (a) 5V Systems and (b) Mixed 5V/3.3V Systems DS063 (v5.1) September 22, 2003 Product Specification XC9500 In-System Programmable CPLD Family ply. Figure 12 5V only and mixed 3.3V/5V systems. ) through program- Pin-Locking Capability The capability to lock the user defined pin assignments dur- ing design changes depends on the ability of the architec- ture to adapt to unexpected changes ...
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... The TMS and TCK pins have dedicated pull-up resistors as specified by the IEEE 1149.1 standard. Boundary Scan Description Language (BSDL) files for the 13. In-system pro- XC9500 are included in the development system and are available on the Xilinx FTP site. Design Security XC9500 devices incorporate advanced data security fea- ...
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... Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable Low Power Mode All XC9500 devices offer a low-power mode for individual macrocells or across all macrocells. This feature allows the device power to be significantly reduced. Each individual macrocell may be programmed in low-power mode by the user ...
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... XC9500 In-System Programmable CPLD Family Combinatorial Logic Propagation Delay = T (a) T PSU Combinatorial Logic P-Term Clock Path Setup Time = T PSU (c) All resources within FB using local Feedback Combinatorial Logic Internal Cycle Time = T ( GCK T GSR T GTS PCO Clock to Out Time = T ...
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... Product Specification XC9500 In-System Programmable CPLD Family implement the design and generate a JEDEC bitmap which can be used to program the XC9500 device. Each develop- ment system includes JTAG download software that can be used to program the devices via the standard JTAG inter- face and a download cable. ...
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... XC9500 In-System Programmable CPLD Family Table 5: XC9500 Device Characteristics Device Circuitry Device Inputs and Clocks Function Block JTAG Controller Revision History The following table shows the revision history for this document. Date Version 3.0 12/14/98 Revised datasheet to reflect new AC characteristics and Internal Timing Parmeters. ...