XC3000 Xilinx Corp., XC3000 Datasheet
XC3000
Related parts for XC3000
XC3000 Summary of contents
Page 1
... Maximum power-down and quiescent current • 100% architecture and pin-out compatible with other XC3000 families • Software and bitstream compatible with the XC3000, XC3000A, and XC3000L families XC3100A combines the features of the XC3000A and XC3100 families: • ...
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... All of these new families are upward-compatible extensions of the original XC3000 FPGA architecture. Any bitstream used to configure an XC3000 device will configure the cor- responding XC3000A, XC3000L, XC3100A, or XC3100L device exactly the same way. The XC3100A and XC3100L FPGA architectures are upward-compatible extensions of the XC3000A and XC3000L architectures ...
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... This feature, called Soft Startup, avoids the potential ground bounce when all out-puts are turned on simultaneously. After start-up, the slew rate of the individual outputs is the XC3000 fam- ily, determined by the individual configuration option. Improvements in the XC3100A and XC3100L ...
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... XC3000 Series Field Programmable Gate Arrays Detailed Functional Description The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Con- figurable Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to ...
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... Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays testing, no soft errors have been observed even in the presence of very high doses of alpha radiation. ...
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... An internal high-impedance pull-up resistor (active by default) prevents unconnected inputs from floating. Unlike the original XC3000 series, the XC3000A, XC3000L, XC3100A, and XC3100L families include the Soft Startup feature. When the configuration process is fin- ished and the device starts up in user mode, the first activa- tion of the outputs is automatically slew-rate limited ...
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... RESET RD - two outputs X and Y November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays resources adjacent to the blocks. Each CLB also has two outputs (X and Y) which may drive interconnect networks. Data input for either flip-flop within a CLB is supplied from the function outputs of the combinatorial logic, or the block input, DI ...
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... XC3000 Series Field Programmable Gate Arrays Flexible routing allows use of common or individual CLB clocking. The combinatorial-logic portion of the CLB uses look-up table to implement Boolean functions. Variables selected from the five logic inputs and two internal block flip-flops are used as table address inputs. The combinato- ...
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... The interconnect buffers are available to propagate signals in either direction on a given general interconnect segment. These bidirectional (bidi) buffers are found adjacent to the switching matrices, above November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Terminal Count ...
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... XC3000 Series Field Programmable Gate Arrays Figure 9: Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional. 7-12 R November 9, 1998 (Version 3.1) ...
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... CLB and IOB inputs and outputs. Figure 11: Switch Matrix Interconnection Options for Each Pin. Switch matrices on the edges are different. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Figure 12: CLB X and Y Outputs. The X and Y outputs of each CLB have single contact, direct access to inputs of adjacent CLBs 7 ...
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... XC3000 Series Field Programmable Gate Arrays Global Buffer Direct Input * Unbonded IOBs (6 Places) Figure 13: XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs. 7-14 Global Buffer Inerconnect Alternate Buffer Direct Input November 9, 1998 (Version 3.1) R ...
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... The global buffer in the upper left die corner drives a common line throughout the FPGA. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays umn are connectable half-length lines. On the XC3020A and XC3120A FPGAs, only the outer Longlines are con- nectable half-length lines ...
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... XC3000 Series Field Programmable Gate Arrays Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as connectable half-length lines ...
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... Figure 18: Design Editor. An extra large view of possible interconnections in the lower right corner of the XC3020A. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long-line bus by apply- ing a Low logic level on its 3-state control line ...
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... XC3000 Series Field Programmable Gate Arrays Crystal Oscillator Figure 18 also shows the location of an internal high speed inverting amplifier that may be used to implement an on-chip crystal oscillator associated with the auxiliary buffer in the lower right corner of the die. When the oscilla- ...
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... The FPGA will then resample RESET and the mode lines before re-entering the Configuration state. During configuration, the XC3000A, XC3000L, XC3100A, and XC3100L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low ...
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... XC3000 Series Field Programmable Gate Arrays A re-program is initiated.when a configured XC3000 series device senses a High-to-Low transition and subsequent >6 s Low level on the DONE/PROG package pin, or, if this pin is externally held permanently Low, a High-to-Low tran- sition and subsequent >6 s Low time on the RESET pack- age pin ...
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... PROM format file by the development system. A compatibility exception precludes the use of an XC2000-series device as the mas- ter for XC3000-series devices if their DONE or RESET are programmed to occur after their outputs become active. The Tie Option defines output levels of unused blocks of a design and connects these to unused routing resources ...
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... XC3000 Series Field Programmable Gate Arrays be used to drive the remaining unused routing, as that might affect timing of user nets. Tie can be omitted for quick breadboard iterations where a few additional milliamps of Icc are acceptable. The configuration bitstream begins with eight High pream- ble bits, a 4-bit preamble code and a 24-bit length count. ...
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... Readback, and vice versa. Note also that each Readback frame has one Start bit (read back as a one) but, unlike in November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays configuration, each Readback frame has only one Stop bit (read back as a zero). The third leading dummy bit men- tioned above can be considered the Start bit of the first frame ...
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... Under normal circumstances, all these FPGAs behave the same way; however, if the bitstream is corrupted, an XC3000 device will always start a new frame as soon as it finds the first 0 after the end of the previous frame, even if the data is completely wrong or out-of-sync. Given suffi- ...
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... PINS RESET Figure 23: Master Serial Mode Circuit Diagram November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge. The SPROM CE input can be driven from either LDC or DONE ...
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... Symbol 1 T DSCK 2 C KDS min in less than 25 ms. If this is not possible, configuration can be delayed by CC has reached 4.0 V (2.5 V for the XC3000L). A very long V may require >6- s High level on RESET, followed by a >6- s Low level on RESET and D – Min Max 60 0 rise time of >100 ms November 9, 1998 (Version 3 ...
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... System Reset Figure 25: Master Parallel Mode Circuit Diagram November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays nal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data, and also changes the EPROM address, until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT ...
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... To data hold RCLK High RCLK Low Notes power-up, V must rise from 2 holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long V non-monotonically rising V CC after V has reached 4.0 V (2.5 V for the XC3000L Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High ...
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... OC Figure 27: Peripheral Mode Circuit Diagram November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays when the byte-wide input buffer has transferred its informa- tion into the shift register, and the buffer is ready to receive new data. The length of the BUSY signal depends on the activity in the UART ...
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... Symbol min in less than 25 ms. If this is not possible, configuration can be delayed by CC has reached 4.0 V (2.5 V for the XC3000L). A very long V may require a >6- s High level on RESET, followed by a >6- s Low level on RESET and D New Byte Min Max T 100 ...
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... RESET Figure 29: Slave Serial Mode Circuit Diagram November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays flows the lead device) on its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge ...
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... Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA. 2. Configuration must be delayed until the INIT of all FPGAs is High power-up, V must rise from 2 holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long V non-monotonically rising V CC after V has reached 4.0 V (2.5 V for the XC3000L). ...
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... Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz. 2. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins. 3. Readback should not be initiated until configuration is complete min max for XC3000L. CCLR November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays ...
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... CC Notes power-up, V must rise from 2 holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms non-monotonically rising V CC after Vcc has reached 4.0 V (2.5 V for XC3000L). 2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration ...
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... R Device Performance The XC3000 families of FPGAs can achieve very high per- formance. This is the result of • A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. • Careful optimization of transistor geometries, circuit design, and lay-out, based on years of experience with the XC3000 family. • ...
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... XC3000 Series Field Programmable Gate Arrays 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 100 XC3100A-3 50 XC3000A-- CLBs CLB Levels: 4 CLBs 2 CLBs Gate Levels: (4-16) (3-12) (2-8) Figure 33: Clock Rate as a Function of Logic ...
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... All internal operation is suspended and output buffers are placed in their high-impedance state with no pull-ups. Different from the XC3000 family which can be powered down to a current consumption of a few micro- amps, the XC3100A draws 5 mA, even in power-down. ...
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... XC3000 Series Field Programmable Gate Arrays Pin Descriptions Permanently Dedicated Pins V CC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on package type) connections to ground. All must be connected. PWRDWN A Low on this CMOS-compatible input stops all internal activity, but retains configuration ...
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... Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays D0-D7 This set of eight pins represents the parallel configuration byte for the parallel Master and Peripheral modes. After configuration is complete, they are user-programmed I/O pins ...
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... XC3000 Series Field Programmable Gate Arrays Pin Functions During Configuration Configuration Mode <M2:M1:M0> SLAVE MASTER- MASTER- SERIAL SERIAL PERIPH HIGH <1:1:1> <0:0:0> <1:0:1> <1:1:0> POWR POWER POWER POWER DWN DWN DWN DWN (I) (I) (I) (I) M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M1 (HIGH) (I) M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) ...
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... V pin. The number of ground pins varies from the XC3020A to the XC3090A Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Description Description = –4.0 mA, V min) ...
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... XC3000 Series Field Programmable Gate Arrays XC3000A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum soldering temperature ( 1/16 in.) SOL Junction temperature plastic T J Junction temperature ceramic Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device ...
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... RESET pad to outputs Notes: 1. Timing is based on the XC3042A, for other devices see timing calculator. 2. The CLB output delay (T CKO Data In hold time requirement (T CKDI November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Speed Grade Symbol Min 1 T ILO 8 ...
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... XC3000 Series Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) 7- ILO T 2 ICK ...
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... This means that pad level changes immediately before the internal clock edge (ik) will not be recognized and T are 3 ns higher for XTL2 when the pin is configured as a user input. PID PTG PICK November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Speed Grade -7 Symbol Min Max 3 T 4.0 ...
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... XC3000 Series Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O Pad Output 3- STATE (OUTPUT ENABLE) OUT DIRECT IN REGISTERED IN PROGRAM CONTROLLED MULTIPLEXER 7- PID T 1 PICK ...
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... V pin. The number of ground pins varies from the XC3020L to the XC3090L Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Description range. CC Description = –4.0 mA, V ...
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... T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Notes: 1. Timing is based on the XC3042A, for other devices see timing calculator. 2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices. 7-48 Description 1 1 Units – ...
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... RESET width (Low) delay from RESET pad to outputs Notes: 1. Timing is based on the XC3042L, for other devices see timing calculator. 2. The CLB output delay (T CKO Data In hold time requirement (T CKDI November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays ...
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... XC3000 Series Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) 7- ILO T 2 ICK ...
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... This means that pad level changes immediately before the internal clock edge (ik) will not be recognized and T are 3 ns higher for XTL2 when the pin is configured as a user input. PID PTG PICK November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Speed Grade Symbol 3 T PID T PTG 4 ...
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... XC3000 Series Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O Pad Output 3- STATE (OUTPUT ENABLE) OUT DIRECT IN REGISTERED IN PROGRAM CONTROLLED MULTIPLEXER 7- PID T 1 PICK ...
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... Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 package. 3. Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Description Description = –8.0 mA, V ...
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... T to L.L. High with pair of pull-up resistors BIDI Bidirectional buffer delay Note: 1. Timing is based on the XC3142A, for other devices see timing calculator. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design option for XC3100A devices. 7-54 Description Speed Grade ...
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... For 5-input functions or base FGM functions, each of these ILO QLO ICK specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and 0.30 ns (-09). November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Speed Grade -4 -3 Symbol Min Max ...
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... XC3000 Series Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) 7- ILO ICK ...
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... This means that pad level changes immediately before the internal clock edge (ik) will not be recognized and T are 3 ns higher for XTL2 when the pin is configured as a user input. PID PTG PICK November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Speed Grade -4 -3 Symbol Min Max Min Max ...
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... XC3000 Series Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O Pad Output 3- STATE (OUTPUT ENABLE) OUT DIRECT IN REGISTERED IN PROGRAM CONTROLLED MULTIPLEXER 7- PID T 1 PICK ...
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... V pin. The number of ground pins varies from the XC3142L to the XC3190L Not tested. Allows undriven pins to float High. For any other purpose, use an external pull-up. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Description range. CC Description = -4 ...
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... T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Notes: 1. Timing is based on the XC3142L, for other devices see timing calculator. 2. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid option for XC3100L devices. 7-60 Description Speed Grade Symbol ...
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... T and T are specified for 4-input functions. For 5-input functions or base FGM functions, each of these ILO QLO ICK specifications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2). November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Speed Grade -3 Symbol Min Max ...
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... XC3000 Series Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) 7- ILO ICK ...
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... Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized. November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Speed Grade -3 ...
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... XC3000 Series Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O Pad Output 3- STATE (OUTPUT ENABLE) OUT DIRECT IN REGISTERED IN PROGRAM CONTROLLED MULTIPLEXER 7- PID T 1 PICK ...
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... R XC3000 Series Pin Assignments Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 208. Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology. ...
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... XC3000 Series Field Programmable Gate Arrays XC3000 Series 64-Pin Plastic VQFP Pinouts XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. XC3030A 1 A0-WS-I/O 2 A1-CS2-I/O 3 A2-I/O 4 A3-I/O 5 A4-I/O 6 A14-I/O 7 A5-I/O 8 GND 9 A13-I/O 10 A6-I/O 11 A12-I/O 12 A7-I/O 13 A11-I/O 14 A8-I/O 15 A10-I/O 16 A9-I/O 17 PWRDN 18 TCLKIN-I/O 19 I/O 20 I/O 21 I/O 22 ...
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... R XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts 68 PLCC XC3020A, XC3030A, XC3030A XC3020A XC3042A 10 10 PWRDN 11 11 TCLKIN-I/O 12 — I/O — — I/O — VCC 19 19 I/O — ...
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... XC3000 Series Field Programmable Gate Arrays XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PLCC Pin Number XC3064A, XC3090A, XC3195A 12 PWRDN 13 TCLKIN-I M1-RDATA 32 M0-RTRIG 33 34 HDC-I ...
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... R XC3000 Series 100-Pin QFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin No. XC3020A TQFP XC3030A PQFP VQFP XC3042A 16 13 GND 17 14 A13-I A6-I A12-I A7 A11-I A8-I A10-I A9-I VCC GND* ...
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... XC3000 Series Field Programmable Gate Arrays XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA PGA Pin XC3042A Pin Number XC3064A Number C4 GND B13 A1 PWRDN C11 C3 I/O-TCLKIN A14 B2 I/O D12 B3 I/O C13 A2 I/O* B14 B4 I/O C14 ...
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... R XC3000 Series 144-Pin Plastic TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts XC3042A Pin XC3064A Number XC3090A 1 PWRDN 2 I/O-TCLKIN 3 I/O* 4 I/O 5 I/O 6 I/O* 7 I/O 8 I/O 9 I/O* 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O* 16 I/O 17 I/O 18 GND 19 VCC 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O* 29 I/O 30 I/O 31 I/O* 32 I/O* 33 I/O 34 I/O* 35 I/O 36 M1-RD 37 ...
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... XC3000 Series Field Programmable Gate Arrays XC3000 Series 160-Pin PQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PQFP Pin XC3064A, XC3090A, PQFP Pin Number XC3195A Number I/O 52 ...
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... R XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin PGA Pin XC3090A, XC3195A Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 B3 I/O C14 C4 I/O B15 B4 I/O D14 A4 I/O C15 D5 I/O E14 C5 I/O B16 B5 I/O D15 A5 I/O C16 C6 I/O D16 D6 I/O F14 B6 I/O E15 A6 I/O E16 ...
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... XC3000 Series Field Programmable Gate Arrays XC3000 Series 176-Pin TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin Pin XC3090A Number Number 1 PWRDWN 45 2 TCLKIN ...
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... R XC3000 Series 208-Pin PQFP Pinouts XC3000A, and XC3000L families have identical pinouts Pin Number XC3090A Pin Number 1 – GND 54 3 PWRDWN 55 4 TCLKIN – ...
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... XC3000 Series Field Programmable Gate Arrays XC3195A PQ208 Pinouts Pin Description PQ208 A9-I/O 206 A10-I/O 205 I/O 204 I/O 203 I/O 202 I/O 201 RDY/BUSY-RCLK-I/O A8-I/O 200 A11-I/O 199 I/O 198 I/O 197 I/O 196 I/O 194 A7-I/O 193 A12-I/O 192 I/O 191 I/O 190 I/O 189 I/O 188 I/O 187 I/O 186 A6-I/O 185 A13-I/O 184 VCC 183 ...
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... XC3164A - XC3190A - XC3195A -2 -1 -09 November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays 84 100 132 Plast. Cer. Plast. Plast. Plast. Plast. Cer. PLCC PGA PQFP TQFP VQFP PGA PGA PC84 PG84 PQ100 TQ100 VQ100 PP132 ...
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... XC3000 Series Field Programmable Gate Arrays Pins Plast. Plast. Plast. Type PLCC VQFP PLCC Code PC44 VQ64 PC68 XC3142L XC3190L Notes Commercial, T Number of Available I/O Pins Max I/O XC3020A/XC3120A 64 XC3030A/XC3130A 80 XC3042A/3142A 96 XC2064A/XC3164A 120 XC3090A/XC3190A 144 XC3195A 176 Ordering Information Example: Device Type ...