HD49335F Renesas Electronics Corporation., HD49335F Datasheet - Page 20

no-image

HD49335F

Manufacturer Part Number
HD49335F
Description
Cds/pga And 10-bit A/d Tg Converter
Manufacturer
Renesas Electronics Corporation.
Datasheet
HD49335F/HF
• MON (D0 to D2 of address H’F4)
• H12Baff (D3 to D6 of address H’F4)
• VD latch (D7 of address H’F4)
Differential Code and Gray Code (D8 to D12 of address H’F4)
• Gray code (D8 to D9 of address H’F4)
• Serial data setting items (D10 to D12 of address H’F4)
Rev.1.0, Feb.25.2004, page 20 of 29
1
Select the pulse which output to pin MON (pin 60).
Select the buffer size which output to pin H1A, H2A (pin 22, 26).
Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer)
DC output code can be change to following type.
Gray Code [1]
0
0
1
1
Setting Bit
Gray_test[0]
Gray_test[1]
Gray_test[2]
1
• Standard data output timing
Gray_test[1]
Low
Low
High
High
When D0 to D2: 0, Fix to Low
D3: 2 mA buffer
D4: 4 mA buffer
D5: 10 mA buffer
D6: 14 mA buffer
Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD falling
1
Address
1
When 2, SP1
When 4, OBP
When 6, CPDM
0
Gray Code [0]
0
1
0
1
Setting Contents
Standard data output timing control signal
(Refer to the following table)
ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
Gray_test[0]
Low
High
Low
High
1
0
0
VD latch
Output Code
Binary code
Gray code
Differential encoded binary
Differential encoded gray
D7 D6 D5
Standard Data Output Timing
Third and fourth
Fourth and fifth
Fifth and sixth
Sixth and seventh
When 1, ADCLK
When 3, SP2
When 5, PBLK
When 7, DLL_test
H12_Buff
STD1[7:0] (L)
D4 D3 D2
MON
D1 D0
STD2[15:8] (H)
D12 D11 D10 D9 D8
Gray_test
Gray code

Related parts for HD49335F