HD49335F Renesas Electronics Corporation., HD49335F Datasheet - Page 23

• Manufacturer Part Number: HD49335F
• Description: Cds/pga And 10-bit A/d Tg Converter
• Manufacturer: Renesas Electronics Corporation.

HD49335F/HF
• CDS_test (D12 of address H’F6)
• Dummy clamp current (D9 to 8 of address H’F7)
• Dummy clamp threshold (D12 to 10 of address H’F7)
Rev.1.0, Feb.25.2004, page 23 of 29
1.
2.
3.
H1
DL_RG
DL_SP1
DL_SP2
DL_ADCLK
DLL step decides the how many divide the 1
cycle of sensor CLK. For reference,
set 1 ns(when 2 ns DLL_current bit = 0,
when 1 set to 1 ns)
Can be set 16 to 64 steps by 4 steps.
Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps)
Can be change each 4 type of pulse 0 to 15 steps with
1 step. (1 ns or 2 ns divide)
Select the 2 ns divide when sensor CLK is less than
15 MHz.
(3) Setting method of DLL
It is testing data. Normally set to 0.
Details are refer to page 12.
Details are refer to page 12.
Steps = 4 + (4
Data = When 0, 1/4
Data = When 0, off
0
10
When 2, 1/16
When 2, +64
When 4, +128
When 6, +192
14
N); possible to set N = 3 to 15
Default
28
when 14 to 22MHz: H'09(40 steps)
when 22 to 50MHz: H'1E(60 steps)
when 50 to 72MHz: H'19(40 steps)
42
Figure 15 Analog Delay (DLL) Circuit Block.
56
When 1, 1/8
When 3, 1/32
When 1, +32
When 3, +96
When 5, +160
When 7, +224
(In phase with H1)
ADCLK(0)
P_ADCLK
ADCLK
P_SP1
P_SP2
(0, 0)
DLL = 64 steps
DLL = 15 steps
DLL = 15 steps
DLL = 15 steps
DLL = 15 steps
(Rising)
(Falling)
Control voltage
AND
PC
DL_ADCLK
DL_SP1
DL_SP2
DL_RG
DLL_C