HD49335F Renesas Electronics Corporation., HD49335F Datasheet - Page 28

• Manufacturer Part Number: HD49335F
• Description: Cds/pga And 10-bit A/d Tg Converter
• Manufacturer: Renesas Electronics Corporation.

HD49335F/HF
Rev.1.0, Feb.25.2004, page 28 of 29
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15 Test_I1 (2)
3.0V
Serial data when CDS single operation mode are following resister specifications.
(Latch timing specification is same as normal mode)
CS
SCK
SDATA
CDS single operating mode
Pin 56(Test2 = Low) Pin 57 is "Don't care" in this mode.
PGA(0) LSB
PGA(1)
PGA(2)
PGA(3)
PGA(4)
PGA(5)
PGA(6)
PGA(7) MSB
Test_I1 (0)
Test_I1 (1)
Resister 0
Low
Low
Low
X
X
t
INT1
47
47
47
ADC_in
tsu
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
47/6
SLP
STBY
Output mode(LINV)
Output mode(MINV)
Output mode(Test0)
SHA-fsel(0)
SHA-fsel(1)
SHSW-fsel(0)
SHSW-fsel(1)
SHSW-fsel(2)
SHSW-fsel(3)
Test_I2 (0)
Test_I2 (1)
33k
0.1
0.1
0.1
CCD signal input
Resister 1
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
High
Low
Low
Low: Normal
High: Sleep
Low: Normal
High: Standby
+
0.1
0.1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PBLK
OBP
CP_DM
ADCK
SP2
SP1
DV
AV
ADC_in
BIAS
VRB
VRT
VRM
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AV
+
47/6
Clamp(0)
Clamp(1)
Clamp(2)
Clamp(3)
Clamp(4)
HGstop-Hsel(0)
HGstop-Hsel(1)
HGain-Nsel(0)
HGain-Nsel(1)
LoPwr
ADSEL
Reset
SS
SS
DD
32
49
Resister 2
1000p
3
31
50
High
Low
Low
Low: Normal
High: Low power
tho
Low: Reset
High: Normal
X
Low:CDSin
High:ADin
30
51
1
29
52
fsck
28
53
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
1
1
27
54
Resister 3
26
55
High
High
Low
HD49335
test
25
56
24 23 22 21 20 19 18 17
57 58 59 60 61 62 63 64
100p
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MON(0)
MON(1)
MON(2)
H12Baff(0)
H12Baff(1)
H12Baff(2)
H12Baff(3)
VD latch
Gray1
Gray2
Gray_ts(0)
Gray_ts(1)
Gray_ts(2)
Resister 4
High
Low
Low
Serial data input
DV
DV
DV
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
SCK
SS
0.1
P_SP1(0)
P_SP1(1)
P_SP2(0)
P_SP2(1)
P_ADCLK(0)
P_ADCLK(1)
P_RG(0)
P_RG(1)
DLL_CK(0)
DLL_CK(1)
DLL_CK(2)
DLL_CK(3)
DLL_current
SS
DD
1,2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset(Normally Hi)
3
2
Resister 5
High
High
Low
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
47/6
1
0
1
1
0
1
1
1
0
0
0
1
0
1
1
1
0.1
Pin changes are not effective with pin61.
DL_SP1(0)
DL_SP1(1)
DL_SP1(2)
DL_SP1(3)
DL_SP2(0)
DL_SP2(1)
DL_SP2(2)
DL_SP2(3)
DL_ADCLK(0)
DL_ADCLK(1)
DL_ADCLK(2)
DL_ADCLK(3)
CDS_test
Unit: R:
Resister 6
to
Camera
signal
processor
High
High
Low
C: F
t
INT2
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
DL_RG_r(0)
DL_RG_r(1)
DL_RG_r(2)
DL_RG_r(3)
DL_RG_f(0)
DL_RG_f(1)
DL_RG_f(2)
DL_RG_f(3)
DMCG(0)
DMCG(1)
Dummy CP(0)
Dummy CP(1)
Dummy CP(2)
Resister 7
High
High
High
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0