MC56F8347 Freescale Semiconductor, Inc, MC56F8347 Datasheet - Page 114

• Manufacturer Part Number: MC56F8347
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

6.5.8.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
This bit selects the alternate function for GPIOC3.
6.5.8.3
This bit selects the alternate function for GPIOC2.
6.5.8.4
This bit selects the alternate function for GPIOC1.
6.5.8.5
This bit selects the alternate function for GPIOC0.
6.5.9
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip.
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Base + $C
Base + $B
RESET
RESET
Read
Write
Read
Write
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User’s Manual)
1 = SS1
0 = INDEX1/TB2 (default)
1 = MISO1
0 = PHASEB1/TB1 (default)
1 = MOSI1
0 = PHASEA1/TB0 (default)
1 = SCLK1
Peripheral Clock Enable Register (SIM_PCE)
Reserved—Bits 15–4
GPIOC3 (C3)—Bit 3
GPIOC2 (C2)—Bit 2
GPIOC1 (C1)—Bit 1
GPIOC0 (C0)—Bit 0
EMI
15
1
15
0
0
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0
14
1
14
0
0
13
13
1
0
0
12
12
1
0
0
11
11
1
0
0
56F8347 Technical Data, Rev.11
10
10
0
0
1
9
0
0
9
1
8
0
0
8
1
7
0
0
7
1
6
0
0
6
1
5
0
0
5
1
4
0
0
4
1
C3
3
0
SPI 1
3
1
Freescale Semiconductor
C2
2
0
SPI 0
2
1
PWMB
C1
1
0
1
1
Preliminary
PWMA
C0
0
0
0
1