HT46R62 Holtek Semiconductor Inc., HT46R62 Datasheet - Page 15

• Manufacturer Part Number: HT46R62
• Description: Ht46r62/ht46c62 -- A/d With Lcd Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
Note:
Rev. 1.70
Program Counter
Interrupt
Prescaler, Divider
WDT, RTC, Time Base
Timer/event Counter
Input/output Ports
Stack Pointer
TO PDF
0
u
0
1
1
nected to the RES pin as short as possible, to
avoid noise interference.
0
u
1
u
1
* Make the length of the wiring, which is con-
RES reset during power-up
RES reset during normal operation
RES Wake-up HALT
WDT time-out during normal operation
WDT Wake-up HALT
Reset Timing Chart
Reset Circuit
RESET Conditions
000H
Disabled
Cleared
Cleared. After master reset,
WDT starts counting
Off
Input mode
Points to the top of the stack
15
Timer/Event Counter
One timer/event counters (TMR) are implemented in the
microcontroller. The Timer/Event Counter contains a
8-bit programmable count-up counter and the clock may
come from an external source or an internal clock
source. An internal clock source comes from f
external clock input allows the user to count external
events, measure time intervals or pulse widths, or to
generate an accurate time base.
There are two registers related to the Timer/Event
Counter; TMR ([0DH]) and TMRC ([0EH]). Two physical
registers are mapped to TMR location; writing TMR puts
the starting value in the Timer/Event Counter register
and reading TMR takes the contents of the Timer/Event
Counter. The TMRC is a timer/event counter control reg-
ister, which defines some options counting enable or
disable and an active edge.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
mode can be used to count the high or low level duration
of the external signal (TMR), and the counting is based
on the internal selected clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag (TF; bit 6 of INTC0). In the pulse width mea-
surement mode with the values of the TON and TE bits
equal to 1, after the TMR has received a transient from
low to high (or high to low if the TE bit is 0 ), it will start
counting until the TMR returns to the original level and
resets the TON. The measured result remains in the
timer/event counter even if the activated transient oc-
curs again. In other words, only 1-cycle measurement
can be made until the TON is set. The cycle measure-
ment will re-function as long as it receives further tran-
sient pulse. In this operation mode, the timer/event
counter begins counting not according to the logic level
but to the transient edges. In the case of counter over-
Reset Configuration
HT46R62/HT46C62
February 14, 2006
SYS
. The