HMP8156 Intersil Corporation, HMP8156 Datasheet - Page 6

• Manufacturer Part Number: HMP8156
• Description: Ntsc/pal Encoder
• Manufacturer: Intersil Corporation

NOTE: Video timing control signals include HSYNC, VSYNC, BLANK and FIELD. The sync and blanking I/O directions are independent;
8-Bit YCbCr Format without 2X Upscaling
When 8-bit YCbCr format is selected and 2X upscaling is not
enabled, the data is latched on each rising edge of CLK2.
The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the
first active data each scan line being Cb data. Overlay data
is latched when the Y input data is latched. The pixel and
overlay input timing is shown in Figure 1.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency
INPUT FORMAT
(OUTPUT)
OL0-OL2,
16-Bit YCbCr,
8-Bit YCbCr
16-Bit RGB,
(INPUT)
24-Bit RGB
BLANK
BLANK
P8-P15
M1, M0
CLK2
BT.656
FIELD is always an output.
or
FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITHOUT 2X UPSCALING
Off
On
Off
On
Off
On
Every rising edge
of CLK2
Rising edge of
CLK2 when CLK
is low.
Rising edge of CLK2 when CLK is low
2nd rising edge of CLK2 when CLK is low
Every rising edge
of CLK2
PIXEL DATA
INPUT PORT SAMPLING
TABLE 5. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING
Cb 0
PIXEL 0
Y 0
OVERLAY DATA
Same edge that
latches Y
Same edge that
latches Y data
Same edge that
latches Y
Cr 0
HMP8156
PIXEL 1
6
Every rising edge
of CLK2
Rising edge of
CLK2 when CLK
is low.
Not Allowed
INPUT SAMPLE
8-Bit YCbCr Format with 2X Upscaling
When 8-bit YCbCr format is selected, the data is latched on
the rising edge of CLK2 while CLK is low. The pixel data
must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the first active data
each scan line being Cb data. Overlay data is latched on the
rising edge of CLK2 that latches Y pixel input data. The pixel
and overlay input timing is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In this mode of operation, CLK is
one-half the CLK2 frequency.
VIDEO TIMING CONTROL (NOTE)
Y 1
Not Available
Cb 2
PIXEL 2
Any rising edge of
CLK2
Rising edge of
CLK2 when CLK
is high.
Rising edge of
CLK2 when CLK
is high.
Either rising
CLK2 edge when
CLK is high
Any rising edge of
CLK2
OUTPUT ON
Y 2
PIXEL N
Ignored
Ignored
INPUT
CLK FREQUENCY
Y N
One-fourth CLK2
One-half CLK2
One-half CLK2
One-half
CLK2
One-half
CLK2
OUTPUT