HMP8156 Intersil Corporation, HMP8156 Datasheet - Page 9

• Manufacturer Part Number: HMP8156
• Description: Ntsc/pal Encoder
• Manufacturer: Intersil Corporation

(OUTPUT)
8-Bit Parallel ITU-R BT.656 Format
When ITU-R BT.656 format is selected, data is latched on
each rising edge of CLK2. Overlay data is latched when the
Y input data is latched. However, the overlay data must
arrive three pixels after its corresponding Y data. The pixel
and overlay input timing is shown in Figure 9.
As inputs, the BLANK, HSYNC, and VSYNC pins are
ignored since all timing is derived from the EAV and SAV
sequences within the data stream. As outputs, BLANK,
OL0-OL2,
(OUTPUT)
(OUTPUT)
OL0-OL2,
BLANK
P8-P15
M1, M0
(INPUT)
(INPUT)
BLANK
BLANK
BLANK
BLANK
CLK2
P0-P15
M1, M0
P0-P24
CLK2
CLK2
CLK
CLK
Cb 2
Y 2
FIGURE 7. PIXEL AND OVERLAY INPUT TIMING - 16-BIT RGB WITH 2X UPSAMPLING
FIGURE 8. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH 2X UPSAMPLING
Cr 2
PIXEL 0
FIGURE 9. PIXEL AND OVERLAY INPUT TIMING - BT.656
Y 3
PIXEL 0
RGB 0
RGB 0
Cb 4
PIXEL 1
Y 4
HMP8156
PIXEL 1
RGB 1
RGB 1
9
HSYNC and VSYNC are output following the rising edge of
CLK2. If the CLK pin is configured as an input, it is ignored. If
configured as an output, it is one-half the CLK2 frequency.
Square pixel operation, overlay processing with internal mix-
ing, and SIF mode 2X upsampling are not supported for the
BT.656 input format. Also, the HSYNC, VSYNC, and BLANK
signals must be configured as outputs.
"FF"
PIXEL N-2
"00"
"00"
PIXEL N-1
"XY"
PIXEL N
RGB N
RGB N
"10"
PIXEL N
"80"
"10"