HMP8156 Intersil Corporation, HMP8156 Datasheet - Page 7

• Manufacturer Part Number: HMP8156
• Description: Ntsc/pal Encoder
• Manufacturer: Intersil Corporation

16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats without
2X Upscaling
When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format
is selected without 2X upscaling, the pixel data is latched on
the rising edge of CLK2 while CLK is low. Overlay data is
also latched on the rising edge of CLK2 while CLK is low.
The pixel and overlay input timing is shown in Figures 3 - 5.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In these modes of operation, CLK is
one-half the CLK2 frequency.
(OUTPUT)
(OUTPUT)
OL0-OL2,
OL0-OL2,
(INPUT)
BLANK
BLANK
(INPUT)
P8-P15
M1, M0
BLANK
BLANK
CLK2
P8-P15
M1, M0
P0-P7
CLK2
CLK
CLK
FIGURE 3. PIXEL AND OVERLAY INPUT TIMING 6-BIT YCBCR WITHOUT 2X UPSCALING
FIGURE 2. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING
Cb 0
PIXEL 0
Cb 0
Y 0
PIXEL 0
PIXEL 1
Cr 0
Y 1
Y 0
Cb 2
PIXEL 2
Y 2
Cr 0
HMP8156
PIXEL 1
7
PIXEL 3
Cr 2
Y 3
16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with 2X
Upscaling
When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format
is selected and 2X upscaling is enabled, data is latched on
the rising edge of CLK2 while CLK is low. Overlay data is
latched on the rising edge of CLK2 while CLK is low. The
pixel and overlay input timing is shown in Figures 6-8
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. CLK is one-fourth the CLK2 fre-
quency.
Y 1
Cb 4
PIXEL 4
Cb 2
Y 4
PIXEL 2
PIXEL 5
Cr 4
Y 5
Y 2
PIXEL N
Cr N-1
PIXEL N
Y N
Y N