IXXBB1 Fujitsu Microelectronics, Inc., IXXBB1 Datasheet - Page 123

• Manufacturer Part Number: IXXBB1
• Description: 32-bit Proprietary Microcontroller Cmos Fr60 Mb91301 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

• Pin Status List (External bus : 32 bit bus width)
Pin no.
18 to 25
45 to 52
55 to 62
64 to 67
76 to 79
8 to 15
1 to 5
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
68
69
70
71
81
82
83
84
P13 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P63
name
Port
PG0
PG1
PG2
PG3
P80
P81
P82
P83
P84
P85
P86
P87
P90
P91
P92
P93
P94
P95
P96
P64
P65
P66
P67
⎯
DQMUU/WR0 DQMUU/WR0 DQMUU/WR0
DQMUL/WR1
DQMLU/WR2
DQMLL/WR3
AN3 to AN0
Specified
D11 to D15
D16 to D23
D24 to D31
SRAS/LBA/
SCAS/BAA
A00 to A07
A08 to A15
A16 to A19
INT0/ICU0
INT1/ICU1
INT2/ICU2
INT3/ICU3
function
A20/SDA0
A21/SCL0
A22/SDA1
A23/SCL1
SWE/WR
SYSCLK
BGRNT
MCLKE
name
MCLK
RDY
BRQ
RD
AS
⎯
DQMUL/WR1
DQMLU/WR2
DQMLL/WR3
Bus width
AN3 to AN0
D11 to D15
D16 to D23
D24 to D31
Function
A00 to A07
A08 to A15
A16 to A19
SYSCLK
MCLKE
name
32 bit
MCLK
PG0
PG1
PG2
PG3
P80
P81
P82
P93
P94
P95
P96
A20
A21
A22
A23
RD
Bus width
AN3 to AN0
D24 to D31
P13 to P17
P20 to P27
A00 to A07
A08 to A15
A16 to A19
At initialization (INIT)
Function
SYSCLK
MCLKE
name
MCLK
8 bit
PG0
PG1
PG2
PG3
P80
P81
P82
P85
P86
P87
P93
P94
P95
P96
A20
A21
A22
A23
RD
Output Hi-Z
Input ready
Output Hi-Z
Input ready
H output
F : H output
Asserted
Negated
H output
Asserted
Negated
Output Hi-Z
Input ready
Output Hi-Z
Input ready
Output Hi-Z
Input ready
Output Hi-Z
Input ready
FF output
input invalid
Output Hi-Z
Input ready
: CLK output
: CLK output
: L output
: L output
Initial
value
P : Previous
F : Output
P : Previous
F : RDY input
P : Previous
F : H output
P : Previous
F : BRQ input
P : Previous
F : H output
P : Previous
F : SYSCLK
F : L output
P : Previous
F : H output
Previous
state held
P : Previous
F : H output
P : Previous
F : H output
P : Previous
F : SWE
P : Previous
F : Address
Previous
state held
P : Previous
F : Normal
state held
state held
output
Sleep
mode
state held
state held
state held
operation
state held
held or
Hi-Z
state held
state held
invalid
state held
state held
state held
output
state held
output
P : Previous
F : Output
Previous
state held
Previous
state held
P : Previous
F : H or L out-
F : L output
P : Previous
F : H output
Previous
state held
H output
H output
Previous
state held
The same as
stated left
input invalid
P : Previous
F : Input
HIZ = 0
state held
held or
Hi-Z
state held
put
state held
state held
ready
MB91301 Series
Stop mode
Output
Hi-Z/
input 0
fixed
Output
Hi-Z/
input 0
fixed
Output
Hi-Z/
input 0
fixed
F : Output
F : Output
Output
Hi-Z
Output
Hi-Z
Output
Hi-Z
Output
Hi-Z/
input 0
fixed
Output
Hi-Z/
input 0
fixed
input
invalid
P : Output
F : Input
HIZ = 1
Hi-Z
Hi-Z
Hi-Z
ready
Output Hi-Z
P : Previous
F : RDY input
L output
BRQ input
Output Hi-Z
F : CLK
Output Hi-Z
Output Hi-Z
Port
Function
Output Hi-Z
Output Hi-Z
Output Hi-Z
Output Hi-Z
Previous
state held
Normal
operation
CS shared
state held
output
Bus released
(BGRNT)
(Continued)
Output Hi-Z
P : Previous
F : RDY input
L output
BRQ input
Previous
state held
F : CLK
H output
F : CLK
Port
Function
F : H output
H output
Previous
state held
Output Hi-Z
Previous
state held
Normal
operation
CS not
shared
state held
output
output
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