AD5560 Analog Devices, Inc., AD5560 Datasheet
AD5560
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AD5560 Summary of contents
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... DUTGND Kelvin sense and alarm span with asymmetrical operation within −22 V/+25 V GENERAL DESCRIPTION The AD5560 is a high performance, highly integrated device power supply consisting of programmable force voltages and measure ranges. This part includes the required DAC levels to set the programmable inputs for the drive amplifier, as well as clamping and comparator circuitry ...
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... Measure Output (MEASOUT) ................................................. 31 V Voltage ................................................................................ 31 MID Force Amplifier Stability ............................................................ 34 Poles and Zeros in a Typical System ........................................ 35 Minimizing the Number of External Compensation Components ................................................................................ 35 Extra Poles and Zeros in the AD5560 ...................................... 35 Compensation Strategies ........................................................... 36 Optimizing Performance for a Known Capacitor Using Autocompensation Mode .......................................................... 36 Adjusting the Autocompensation Mode ................................. 37 ...
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... Changes to Table 2 .......................................................................... 13 Changes to Table 3 .......................................................................... 15 Changes to Open-Sense Detect (OSD) Alarm and Clamp ........ 27 Changes to Figure 53 ...................................................................... 30 Change to gm Maximum Rating, Table 13 .................................. 34 Changes to Table 19 ........................................................................ 46 Changes to Bit 7, Bit 8 Functions, Table 21.................................. 48 Changes to Power Supply Decoupling Section ........................... 59 11/08—Revision 0: Initial Version Rev Page AD5560 ...
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... AD5560 FUNCTIONAL BLOCK DIAGRAM 100kΩ 25kΩ 6kΩ Figure 1. Rev Page 07779-001 ...
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... Measured at 1 kHz, at output of FORCE. Sense resistors are trimmed to within 1%, nominal ±500 RSENSE kΩ ±5 μA current range. kΩ ±25 μA current range. kΩ ±250 μA current range. Ω ±2.5 mA current range. Ω ±25 mA current range. AD5560 = CC /AV , includes supplies; SS voltage drop. SENSE ...
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... AD5560 Parameter Min Measure Current Ranges MEASURE CURRENT 1 Differential Input Voltage Range −0.64 −0.7 1 Output Voltage Span Offset Error −1 1 Offset Error Tempco Offset Error −1.5 1 Offset Error Tempco Offset Error −1.5 1 Offset Error Tempco Offset Error −3 1 Offset Error Tempco Gain Error − ...
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... +25 mA Rev Page AD5560 Test Conditions/Comments Standard deviation = 12 μV/° kHz, at MEASOUT, inputs grounded. Referred to MV input, nominal supply (±16.5 V, 0x8000 offset DAC). Referred to MV input, low supply (−25 V/+8 V, 0xD4EB offset DAC). Referred to MV input, high supply (−5 V/+28 V, 0xD1D offset DAC) ...
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... AD5560 Parameter Min Leakage Current −2.5 1 Leakage Current Tempco Path On Resistance 1 Pin Capacitance SYS_DUTGND Voltage Range AV SS Path On Resistance CURRENT CLAMP Clamp Accuracy Programmed clamp value Programmed clamp value 1 VCLL to VCLH 2 1 VCLL VCLH Clamp Activation Response Time ...
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... V +1 LSB 16 Bits LSB 16 Bits LSB 3.5 6 μs Rev Page AD5560 Test Conditions/Comments 8 V step 8.8 Ω 0.22 μF, full dc DUT DUT load step Ω 0.22 μF, full dc DUT DUT load step 33.3 Ω 0.22 μF, full dc DUT DUT load. ...
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... AD5560 Parameter Min 1 Slew Rate 1 Digital-to-Analog Glitch Energy 1 Glitch Impulse Peak Amplitude REFERENCE INPUT VREF DC Input Impedance 1 VREF Input Current −10 1 VREF Range 2 COMPARATOR Error −7 VOLTAGE COMPARATOR 1 Propagation Delay 1 Error −12 CURRENT COMPARATOR 1 Propagation Delay 1 Error −1.5 MEASURE OUTPUT, MEASOUT ...
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... Of programmed value kHz. dB − 100 kHz. dB − 100 kHz. dB − 100 kHz. dB − 100 kHz. dB − 100 kHz. dB − 100 kHz. dB − 100 kHz. AD5560 = 1 kΩ. x ≥ ≥ ...
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... AD5560 Parameter Min ΔMeasured Current/ΔHCAV x SS ΔMeasured Voltage/ΔAV DD ΔMeasured Voltage/ΔAV SS ΔMeasured Voltage/ΔHCAV x DD ΔMeasured Voltage/ΔHCAV x SS ΔForced Voltage/ΔDV CC ΔMeasured Current/ΔDV CC ΔMeasured Voltage/Δ Guaranteed by design and characterization, not subject to production test. 2 Clamps disabled. ...
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... BUSY rising edge to LOAD falling edge LOAD rising edge to FORCE output response time LOAD rising edge to current range response 200µ OUTPUT V (MIN) – PIN C LOAD 50pF 200µ Figure 3. Load Circuit for CMOS AD5560 = 25°C to 90°C, J (MAX ...
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... AD5560 SCLK SYNC t 5 DB23 SDI BUSY 1,3 LOAD FORCE EXTFORCE1 1 EXTFORCE2 2,3 LOAD FORCE EXTFORCE1 2,3 EXTFORCE2 RESET BUSY 1 LOAD ACTIVE DURING BUSY. 2 LOAD ACTIVE AFTER BUSY. 3 LOAD FUNCTION IS AVAILABLE VIA CLEN OR HW_INH AS DETERMINED BY DPS REGISTER 2. SCLK SYNC SDI DB23 INPUT WORD SPECIFIES ...
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... JC JC Airflow (Uniform (Local (LFPM) θ Heating) Heating 4.91 200 37.2 400 35.7 0 12.2 1 4.91 200 11.1 400 9.5 N/A N/A 1 4.91 = 30°C, total power = 8 distributed, 7 COLD PLATE ~6.2°C/W giving ~T CA AD5560 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C < 90°C. Thermal J ...
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... Accurate Ground Reference for Applied Voltage Reference PIN AD5560 8 TOP VIEW (Not to Scale) 9 EXPOSED PAD ON TOP Figure 6. Pin Configuration Rev Page EXTMEASIH2 48 47 ...
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... HCAV GPO Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT The exposed pad is internally connected to AV System Device Under Test Ground Pin. See the DPS Register 2 in Table Rev Page AD5560 ...
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... AD5560 TYPICAL PERFORMANCE CHARACTERISTICS 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 0 10,000 20,000 30,000 40,000 CODE Figure 7. Force Voltage Linearity vs. Code, V 2.0 1.5 1.0 0.5 MEASOUT GAIN = 0.2 0 –0.5 –1.0 –1.5 MEASOUT GAIN = 1 –2.0 0 10,000 20,000 30,000 40,000 CODE Figure 8. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1, MEASOUT Gain = 0.2, Nominal Supplies MEASOUT GAIN = 0.2 ...
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... EXTFORCE1B EXTMEASIH1 SENSE EXTFORCE1C EXTMEASIH2 SYS_FORCE EXTFORCE2A EXTMEASIL SYS_SENSE COMBINED LEAKAGE – STRESS VOLTAGE ( STRESS EXTFORCE1A EXTFORCE2B FORCE EXTFORCE1B EXTMEASIH1 SENSE EXTFORCE1C EXTMEASIH2 SYS_FORCE EXTFORCE2A EXTMEASIL SYS_SENSE COMBINED LEAKAGE TEMPERATURE (° STRESS AD5560 60,000 ...
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... AD5560 0.15 EXTFORCE1A EXTFORCE2B EXTFORCE1B 0.10 EXTMEASIH1 SENSE EXTFORCE1C 0.05 EXTMEASIH2 SYS_FORCE EXTFORCE2A 0 EXTMEASIL SYS_SENSE –0.05 –0.10 –0.15 –0.20 – STRESS VOLTAGE (V) Figure 19. Leakage Current vs. Stress Voltage 0 STRESS 0.7 0.6 EXTFORCE1A 0.5 EXTFORCE2B EXTFORCE1B EXTMEASIH1 0.4 SENSE EXTFORCE1C EXTMEASIH2 0.3 SYS_FORCE EXTFORCE2A EXTMEASIL 0.2 SYS_SENSE 0 TEMPERATURE (° ...
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... LOW TEMPERATURE (°C) CH1 p-p 27mV CH1 AREA 10.92µVs FORCE SYNC 50mV B M200µs A CH3 W T 10. LOAD CH1 p-p 16mV CH1 AREA –5.336µVs FORCE SYNC 50mV M200µs A CH3 10.4% W LOAD AD5560 85 1. μF Load 1. μF Load ...
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... AD5560 FORCE 1 SYNC 3 CH1 50mV B M200µ 10.4% CH3 Figure 31. Range Change EXTFORCE2, Safe Mode μF Load LOAD FORCE 1 SYNC 3 CH1 50mV M200µs T 10.4% CH3 5V Figure 32. Range Change EXTFORCE2 to 25 mA, Safe Mode μF Load LOAD ...
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... +16.25V –16.25V REF OFFSET DAC = 0x8000 EXTFORCE1/1.2A RANGE LOAD 0 TO 3.7V STEP C = 10µF CERAMIC LOAD AUTOCOMP MODE 0x9680 MEASOUT GAIN 1, MI GAIN 20 BUSY B 5V CH2 1V M4µs A CH3 CH4 10V Autocompensation Mode AD5560 2.9V 2.9V 2.9V ...
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... AD5560 MEASOUT – 25° +16.25V –16.25V REF OFFSET DAC = 0x8000 EXTFORCE1/1.2A RANGE LOAD 0 TO 3.7V STEP C = 10µF CERAMIC 2 LOAD SAFE MODE MEASOUT GAIN 1, MI GAIN CH1 5V CH2 1V M20µ 4.6% CH3 5V CH4 10V Figure 43 ...
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... FREQUENCY (Hz) Figure 50. ACPSRR of HCAV x vs. Frequency DD 0 –20 FOH –40 –60 –80 MV: GAIN 0 –100 –120 FOH DV –140 1M 10M 10 1M 10M Rev Page AD5560 MI: GAIN 0 MV: GAIN 0 = +5.25V +16.5V –16. 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 51. ACPSRR of HCAV x vs. Frequency SS 10M ...
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... AD5560 TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in millivolts (mV) or percentage of full-scale range (%FSR). Gain Error Gain error is the difference between full-scale error and zero- scale error expressed in percentage of full-scale range (%FSR). Gain Error = Full-Scale Error − ...
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... THEORY OF OPERATION The AD5560 is a single-channel, device power supply for use in semiconductor automatic test equipment. All the DAC levels required to operate the device are available on chip. This device contains programmable modes to force a pin vol- tage and measure the corresponding current (FVMI) covering a wide current measure range ± ...
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... These can be used for diagnostic purposes to determine the thermal gradients across the die and across a board containing many AD5560 devices. When selected, the anode of these diodes is connected to GPO and the cathode to AGND. The AD5560 evaluation board uses the ON Semiconductor® ...
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... The AD5560 has three compensation modes: safe mode, autocompensation mode, and manual compensation mode, all of which are described in more detail in the Force Amplifier Stability section. The range of suggested compensation capacitors allows optimum performance for any capacitive load from 160 μ ...
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... COMPENSATION FOR GANG MODE SENSE When ganging, the slave devices should be set to the fastest response. When slaves are in FI mode, the AD5560 force amplifier over- rides other compensation settings to enforce C and g therefore, readback won’t show that the signals inside the force DUT amplifier actually change ...
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... DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN There are three types of temperature sensors in the AD5560. • The first is a temperature sensor available on the MEASOUT pin and expressed in voltage terms. Nominally at 25°C, this sensor reads 1. has a temperature coefficient of 4.7 mV/°C. This sensor is active during power-down mode. ...
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... Do not allow the MEASOUT output range to exceed the AIN range of the ADC. 3 For the purposes of sharing ADCs among multiple DPS channels, note that the multiplexer is not absolutely necessary because the AD5560 MEASOUT path has a tristate mode. approximately 2 V footroom to AV AVDD/AVSS Power Supply Rails section for more information ...
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... DAC 2/8.25) × (OFFSET DAC VOLTAGE) OS 8.25R 2R 2R 8.25R V OSD DAC IN MI_x10 MEASURE CURRENT MI_x20 mi_gain 2R 2R MEASURE VOLTAGE AMP SENSE Rev Page att R 5R MIN att 5R 1kΩ mi att 5R 1kΩ att mv att 5R AD5560 MEASOUT tri ...
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... AD5560. Autocompensation Mode Using this mode, the user inputs the C R the AD5560 decides the most appropriate compensation scheme for these load conditions. The compensation chosen is for an optimum tradeoff between ac response and stability. Manual Compensation Mode This mode allows access to all of the internal programmable parameters to configure poles/zeros, which affect the dynamic performance of the loop ...
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... The Effect The output of the AD5560 passes through a sense resistor to the DUT. Coupled with the load capacitor, this sense resistor can act as a low-pass filter that adds phase shift and decreases phase margin (particularly in the low current ranges where the sense resistors are large) ...
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... COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Maximum Value If the AD5560 has to be stable in a range of load capacitance from no load capacitance to an upper limit, then select manual compensation mode and, in Compensation Register 2, set the parameters according to the maximum load capacitance listed in Table 14 ...
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... This ends the algorithm ADJUSTING THE AUTOCOMPENSATION MODE The autocompensation algorithm assumes that there is 1 Ω of resistance (R ) from the AD5560 to the DUT particular C application has resistance that differs greatly from this, then it is likely that the autocompensation algorithm is nonoptimal. If using the autocompensation algorithm as a starting point, ...
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... AD5560 The transfer function for these 16-bit DACs is ⎛ DAC CODE = × × ⎜ ⎜ VCLH , VCLL . 5 125 V REF 16 ⎝ 2 ⎛ ⎞ OFFSET _ DAC _ CODE + ⎜ ⎟ DUTGND ⎝ ⎠ The transfer function for the clamp current value is ⎛ DAC CODE × ...
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... SS HCAV drop should also be factored into the supply rail calculation. The AD5560 is designed to settle fast into large capacitive loads in high current ranges; therefore, when slewing, the device draws 2× to 3× the current range from the HCAV supplies. When choosing supply rails, ensure that they are capable of supplying each DPS channel with sufficient current to slew ...
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... V/μs, 0.875 V/μs, 0.750 V/μs, 0.625 V/μs, 0.5 V/μs, 0.4375 V/μs, 0.35V μs, and 0.313 V/μs. Ramp Function Included in the AD5560 is a ramp function that enables the user to apply a rising or falling voltage ramp to the DUT. The user supplies a clock, RCLK, to control the timing. ...
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... ALARM RAMP COMPLETE? YES RETURN TO TERMINATE RAMP NORMAL MODE Figure 56. Flow Chart for Ramp Function Rev Page PROGRAM CLOCK DIVIDER WRITE NEW FIN ×1 DAC VALUE CALCULATE NEXT DAC CODE LOAD DAC DO NOT LOAD DAC. RETAIN PREVIOUS VALUE AD5560 ...
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... The serial word is 24 bits long. The serial interface works with both a continuous and a burst (gated) serial clock. Serial data applied to SDI is clocked into the AD5560 by clock pulses applied to SCLK. The first falling edge of SYNC starts the write cycle. At least 24 falling clock edges must be applied to SCLK to clock in 24 bits of data before SYNC is taken high again ...
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... When the write to one of the x1 registers is complete, the calculation process begins. The user is free to write to another register provided that the write operation does not finish until the first stage calculation is complete, that is, 600 ns after the completion of the first write operation. Rev Page AD5560 ...
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... AD5560 CONTROL REGISTERS DPS AND DAC ADDRESSING The serial word assignment consists of 24 bits, as shown in Table 16. All write-to registers can be read back. There are some read-only registers (Address 0x43 and Address 0x44). DAC x2 registers are not available for readback. Table 16. Serial Word Assignment ...
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... MEASOUT high-Z. Connect MEASOUT to I SENSE. Connect MEASOUT to V SENSE. Connect MEASOUT to K SENSE. TSENSE. Connect MEASOUT to Connect MEASOUT to DUTGND SENSE. Connect MEASOUT to diagnostic functions: DIAG A (see Address 0x7). Connect MEASOUT to diagnostic functions: DIAG B (see Address 0x7). Rev Page AD5560 ...
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... AD5560 Table 19. DPS Register 2 Address Default 0x3 0x0000 Bit Name 15 SF0 14 SR[2: GPO 10 SLAVE, GANGIMODE 9 8 INT10K 7 Guard high-Z 6:0 Unused Data Bits, MSB First Function System force and sense line addressing, SF0. Bit SF0 addresses each of the different combinations of switching the system force and sense lines to the force and sense pins at the DUT ...
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... The AD5560 has three compensation modes. The power-on default mode is into any load. Use Compensation Register 1 to configure the device for autocompensation, where the user inputs the CDUT and ESR bits, and the AD5560 chooses the most appropriate compensation scheme for these load conditions. Table 20. Compensation Register 1 ...
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... Data Bits, MSB First Function The AD5560 can be manually configured to compensate the force amplifier into a wide range of load conditions. When this bit is high, manual compensation mode is active, and it overrides the settings of Compensation Register 1. Readback when in manual compensation mode returns the compensation settings loaded to the force amplifier and loaded to this register ...
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... The disable GRDALM, DUTALM and OSALM alarm functions share one open-drain KELALM alarm pin. These bits allow users to choose if they wish to have all or any information flagged to the KELALM alarm pin. Set to 0. Rev Page AD5560 ...
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... AD5560 Table 23. Diagnostic Register Address Default 0x7 0x0000 Bit Name 15 DIAG select[3: TSENSE select[3: Data Bits, MSB First Function DIAG select selects the set of diagnostic signals that can be made available on MEASOUT. First, use MEASOUT addressing (DPS Register 1) to select either the DIAG A or the DIAG B node to be made available on MEASOUT. ...
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... Amplifier EXTFORCE1 0 EXTFORCE1 1 EXTFORCE1 2 EXTFORCE1 3 EXTFORCE2 0 EXTFORCE2 1 EXTFORCE2 2 EXTFORCE2 3 Set to 0. Rev Page AD5560 1A-1 1A-2 2A (similar location to VPTAT high for EXTFORCE2 range) 1B-1 (similar location to VPTAT high for EXTFORCE1 range) 1B-2 2B 1C-1 1C-2 Enabled Stage All stages EXTFORCE1C EXTFORCE1B EXTFORCE1A All stages Reserved EXTFORCE2B EXTFORCE2A ...
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... AD5560 Table 24. Other Registers Address Register 0x8 FIN DAC x1 0x9 FIN DAC m 0xA FIN DAC c 0xB Offset DAC x 0xC OSD DAC x 0xD CLL DAC x1 0xE CLL DAC m 0xF CLL DAC c 0x10 CLH DAC x1 0x11 CLH DAC m 0x12 CLH DAC c 0x13 CPL DAC x1 5 μA range 0x14 CPL DAC m 5 μ ...
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... LSBs (775 mV) step. 0x0001 0000 0000 D7 to D0. D7:D0 set the RCLK divider. 0000 0000 = ÷ 1 0000 0001 = ÷ 1 0000 0010 = ÷ 2 0000 0011 = ÷ 3 … 1111 1111 = ÷ 255 0x0000 0xFFFF to enable. 0x0000 0x0000 to interrupt. Rev Page AD5560 ...
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... AD5560 Table 25. Alarm Status and Clear Alarm Status Register Address Register Default 0x43 Alarm status 0x0000 0x44 Alarm status 0x0000 and clear alarm 0x45 CPL DAC x1 0x0000 0x46 CPL DAC m 0xFFFF 0x47 CPL DAC c 0x8000 0x48 CPH DAC x1 0xFFFF 0x49 CPH DAC m ...
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... READBACK MODE The AD5560 allows data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the DAC register (x2 calibrated register). To read back contents of a register necessary to write the R/ W bit, address the appropriate register, and fill the data bits with all zeros ...
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... AD5560 Table 26. AD5560 Truth Table of Switches Reg Bit Name Bit SW1 System Gain0, X Control Gain1 Register FINGND CPO DPS Register SW-INH I2, I1, I0 000 X 001 X 010 X 011 X 100 X 101 X 110 X CMP1, CMP0 ...
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... LOW CURRENT, HIGH VOLTAGE Figure 57. Example of Using the Extra Supply Rails Within the AD5560 to Achieve Multiple Voltage/Current Ranges x SUPPLIES internal pull-up resistors between the supplies (see Figure 57). SS Using diodes here allows a more flexible use of supplies and , provide power SS can minimize the amount of supply switching required ...
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... ADR445 5 ±0.04 1 Subset of the possible references suitable for use with the AD5560. See five feedforward capacitor input pins, all capacitor inputs may be used only if the user intends to drive large variations of DUT load capacitances. If the DUT load capacitance is known and doesn’t change for all combinations of voltage ranges and test conditions, then it is possible only one set of C required ...
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... AD5560 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5560 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device ...
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... Model Temperature Range AD5560JSVUZ 25° AD5560JSVUZ-REEL T = 25° EVAL-AD5560EBUZ junction temperature RoHS Compliant Part. ©2008-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.675 1.20 0.872 5.95 BSC ...