AD5560 Analog Devices, Inc., AD5560 Datasheet - Page 13

• Manufacturer Part Number: AD5560
• Description: 1.2 A Programmable Device Power Supply With Integrated 16-bit Level Setting Dacs
• Manufacturer: Analog Devices, Inc.

TIMING CHARACTERISTICS
HCAV
maximum specifications, unless otherwise noted).
Table 2. SPI Interface
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LOAD TIMING
1
2
3
4
5
6
TIMING DIAGRAMS
UPDATE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications.
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
See Figure 4 and Figure 5.
This is measured with the load circuit shown in Figure 2.
This is measured with the load circuit shown in Figure 3.
4
5, 6
t
t
t
t
16
17
18
19
DD
x ≤ AV
1, 2, 3
TO OUTPUT
SS
Figure 2. Load Circuit for Open Drain
PIN
+ 33 V, HCAV
DV
to 2.7 V
600
25
10
10
10
15
5
5
4.5
40
1.5
280
25
400
250
45
30
20
150
0
150
150
C
CC
LOAD
50pF
= 2.3 V
R
= t
R
SS
F
2.2kΩ
LOAD
= 2 ns (10% to 90% of DV
x ≥ AV
DV
DV
to 3.3 V
600
20
8
8
10
15
5
5
4.5
35
1.5
280
20
400
250
35
30
20
150
0
150
150
CC
CC
= 2.7 V
SS
, AV
V
DD
OL
≥ 8 V, AV
DV
600
20
8
8
10
15
5
5
4.5
30
280
10
250
25
30
20
150
0
150
150
to 5.5 V
1.5
400
CC
) and timed from a voltage level of 1.2 V.
CC
= 4.5 V
Rev. B | Page 13 of 60
SS
≤ −5 V, |AV
Unit
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs max
ns max
ns min
μs max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
DD
− AV
TO OUTPUT
Description
Channel update cycle time
SCLK cycle time; 60/40 duty cycle
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time
24
Data setup time
Data hold time
SYNC rising edge to BUSY falling edge
BUSY pulse width low for DAC x1 write
BUSY pulse width low for other register write
RESET pulse width low
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
SYNC rising edge to SDO high-Z
LOAD pulse width low
BUSY rising edge to force output response time
BUSY rising edge to LOAD falling edge
LOAD rising edge to FORCE output response time
LOAD rising edge to current range response
SS
th
| ≥ 16 V and ≤ 33 V, V
SCLK falling edge to SYNC rising edge
PIN
C
LOAD
50pF
Figure 3. Load Circuit for CMOS
200µA
200µA
I
I
OL
OL
REF
= 5 V (T
V
OH
(MIN) – V
J
= 25°C to 90°C,
2
OL
AD5560
(MAX)