ADN2865 Analog Devices, Inc., ADN2865 Datasheet
ADN2865
Related parts for ADN2865
ADN2865 Summary of contents
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... The ADN2865 have many optional features available via an I interface, e.g. the user can read back the data rate that the ADN2865 is locked on to, or the user can set the device to only lock to one particular data rate if provisioning of data rates is required. ...
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... ADN2865 TABLE OF CONTENTS Specifications..................................................................................... 3 Jitter Specifications....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 7 ESD Caution.................................................................................. 7 Timing Characteristics..................................................................... 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ............................................. Interface Timing and Internal Register Description........... 12 Terminology .................................................................................... 16 Jitter Specifications ......................................................................... 17 Jitter Generation ......................................................................... 17 Jitter Transfer............................................................................... 17 Jitter Tolerance ...
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... PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2865 input stage. = 0.47 μF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 2 F ...
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... ADN2865 Parameter DATA RATE READBACK ACCURACY Coarse Readback Fine Readback POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT OPERATING TEMPERATURE RANGE JITTER SPECIFICATIONS VCC = MIN MAX MIN MAX unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking ...
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... F t 600 SU;STO t 1300 BUF Optional lock to REFCLK mode @ REFCLKP or REFCLKN 12 Rev. PrA | Page ADN2865 Typ Max Unit 350 600 mV 700 1200 mV VCC V VCC − 0.35 VCC − 0.3 V TBD ps TBD ps 320 400 mV 1475 mV V 1200 ...
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... ADN2865 Parameter Input Low Current LVTTL INPUT TIMING Setup Time (Sync Mode) Hold Time (Sync Mode) Setup Time (Align Mode) Hold Time (Align Mode) LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage Conditions Min 0.4 V − (see Figure 3), 1.25Gb/s 3 ...
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... Exposure to absolute 4.2 V maximum rating conditions for extended periods may affect VEE − 0.4 V device reliability. VCC + 0.4 V 125°C THERMAL CHARACTERISTICS −65°C to +150°C Thermal Resistance 300°C 56-LFCSP, 4-layer board with exposed paddle soldered to VEE θ = 28°C/W JA Rev. PrA | Page ADN2865 ...
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... ADN2865 TYPICAL PERFORMANCE CHARACTERISTICS 100 1k R (Ω) TH Figure 2. LOS Comparator Trip Point Programming 1000 100 10 1 0.1 10k 100k 1 Rev. PrA | Page Preliminary Technical Data ADN2812 TOLERANCE SONET REQUIREMENT MASK SONET OBJECTIVE MASK EQUIPMENT LIMIT 10 100 ...
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... TXDATAP / OUTP V CML OUTN OUTP–OUTN V 0V Figure 4. Rx Output Timing Tssu Figure 5. Tx Input Timing (Sync Mode) Figure 6. Tx Input Timing Align Mode DIFF Figure 75. Single-Ended vs. Differential Output Specifications Rev. PrA | Page ADN2865 Tsh 04228-0-002 V SE ...
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... ADN2865 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Preliminary Technical Data Figure 86. Pin Configuration Rev. PrA | Page ...
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... Power for LVDS Drivers Differential receive data output. (LVDS) Differential receive data output. (LVDS) Differential receive data output. (LVDS) Differential receive data output. (LVDS) Differential receive data output. (LVDS) Differential receive data output. (LVDS) Rev. PrA | Page (LVDS) (LVDS) (LVDS) (LVDS) ADN2865 ...
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... ADN2865 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 MSB = 1 S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 A5 SCK S SLADDR[4... SDA t LOW SCK t S SLAVE ADDRESS [6... Figure 9. Slave Address Configuration ...
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... Bus Bus 0 Datarate CLK CLK Range Holdover Holdover Mode 2A Mode HI_CODE[0] Datarate Measurement Coarse Rate Complete Readback LSB Measuring datarate x COARSE_RD[ Measurement complete ADN2865 D0 LSB LSB LSB COARSE_RD[1] COARSE_RD[ 0] LSB Lock to Reference 0 Boost Output HI_CODE[1] LO_CODE[1] LO_CODE[0] ...
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... System Reset D5 D4 Write a 1 followed by Set 0 to reset ADN2865 to 0 Signal Degrade Mode Disable Signal Degrade Set Mode Enable Signal Degrade Mode Initiate PRBS 0=Normal 0 Write a 1 followed by 0 operation ...
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... Mode Control Full Range (12.3M- 2.7G) 1= Limited Range D4 D3 Set to 0 Set to 0 Rev. PrA | Page ADN2865 D0 Set to 0 Clock Holdover Clock Holdover Mode 2A Mode Set to 1 for Clock Set to 1 for Clock Holdover Mode 2A Holdover Mode 2B CDR Mode ...
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... Single-Ended vs. Differential AC coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc biased to a common- mode potential of ~2.5 V. Driving the ADN2865 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure shows a binary signal with an average value equal to the common-mode potential and instantaneous values both above and below the average value ...
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... Preliminary Technical Data JITTER SPECIFICATIONS The ADN2865 CDR is designed to achieve the best bit-error- rate (BER) performance and exceeds the jitter transfer, genera- tion, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where bit period ...
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... ADN2865 THEORY OF OPERATION The ADN2865 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops, which share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter ...
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... The jitter accommodation is roughly 0 this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 3 MHz at OC-48. Rev. PrA | Page ADN2865 ...
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... COUNTER SERIALISER Figure 21. Align Mode Operation FREQUENCY ACQUISITION The ADN2865 acquires frequency from the data over a range of data frequencies from 12.3 Mb/s to 2.7 Gb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, LOL is asserted. This initiates a frequency acquisition cycle ...
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... This hysteresis is shown in Figure 22. Static LOL Mode The ADN2865 implements a static LOL feature, which indicates if a loss of lock condition has ever occurred and remains asserted, even if the ADN2865 regains lock, until the static LOL 2 bit is manually reset. The I C register bit, MISC[4], is the static LOL bit ...
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... Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2865 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long supporting the 7-bit addresses plus the R/W bit. The ADN2865 has 8 subaddresses to enable the user-accessible internal registers (see Table 6 through Table 15) ...
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... The two uses of the reference clock are mutually exclusive. The reference clock can be used either as an acquisition aid for the ADN2865 to lock onto data measure the frequency of the incoming data to within 0.01%. (There is the capability to measure the data rate to approximately ±10% without the use of a reference clock ...
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... MHz. CTRLA[5:2] would be set to [0101], that is, 5, because 5 622.08 Mb/s/19.44 MHz = 2 In this mode, if the ADN2865 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2865 is operating in lock to reference mode, if the user ever changes the reference frequency, the F ...
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... C Interface 2 C interface to In FDDI Mode, the output of the ADN2865 is squelched until the device has acquired lock of the subharmonic input. This causes all zeros to be transmitted out of the 2865 until lock has been achieved. Once locked, the outputs are enabled and begin transmitting data ...
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... PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2865 VCC pins. If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pins 7,45 & ...
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... PDJ pspp < 0.01 UI p-p typical the rise time, which is equal to 0.22/BW, r where BW ~ 0.7 (bit rate). Note that this expression for t The output rise time for the ADN2865 is ~100 ps regardless of data rate. Rev. PrA | Page –t/τ (1 − therefore, τ = 12t ...
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... ADN2865 are dc-coupled, care must be taken not to violate the input range and common-mode level require- ments of the ADN2865 (see Figure through Figure ). If dc coupling is required, and the output levels of the TIA do not adhere to the levels shown in Figure , then level shifting and/or an attenuator must be between the TIA outputs and the ADN2865 inputs ...
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... PIN – NIN = NIN Figure 32. Minimum Allowed DC-Coupled Input Levels = 10mV AT SENSITIVITY V = 5mV MIN 2.3V MIN CM (DC-COUPLED) Rev. PrA | Page × PIN – NIN = 2.0V MAX PP SE PIN V = 1.0V MAX (DC-COUPLED) NIN Figure 33. Maximum Allowed DC-Coupled Input Levels ADN2865 = 2.3V ...
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... ADN2865 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 18. Look-Up Table Code F Code MID 0 5.1934e+ 5.1930e+ 5.2930e+ 5.3989e+ 5.5124e+ 5.6325e+ 5.7612e+ 5.8995e+ 6.0473e+ 6.2097e+ ...
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... Rev. PrA | Page ADN2865 Code F MID 264 1.5481e+09 265 1.5897e+09 266 1.6338e+09 267 1.6813e+09 268 1.7328e+09 269 1.7888e+09 270 1.8499e+09 271 1.9165e+09 272 1 ...
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... OUTLINE DIMENSIONS ORDERING GUIDE Model Temperature Range ADN2865ACP −40°C to 85°C ADN2865ACP-RL −40°C to 85°C ADN2865ACP-RL7 −40°C to 85°C Figure 34. 56-Lead Frame Chip Scale Package [LFCSP] (CP-56) Dimensions shown in millimeters Package Description 56-LFCSP 56-LFCSP, tape-reel, 2500 pcs 56-LFCSP, tape-reel, 1500 pcs Rev ...
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... Preliminary Technical Data NOTES Rev. PrA | Page ADN2865 ...