ADN2865 Analog Devices, Inc., ADN2865 Datasheet - Page 12

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ADN2865

Manufacturer Part Number
ADN2865
Description
Continuous Rate 12.3mb/s To 2.7gb/s Clock And Data Recovery Ic W/loop Timed Serdes
Manufacturer
Analog Devices, Inc.
Datasheet
ADN2865
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
SDA
SCK
START BIT
S
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
S
SLAVE ADDR, LSB = 0 (WR)
A6
SDA
SCK
SLAVE ADDRESS
A5
S
t
F
SLADDR[4...0]
S
MSB = 1
SLAVE ADDR, LSB = 0 (WR) A(S)
1
t
t
LOW
HD;STA
A(S)
SLAVE ADDRESS [6...0]
t
1
HD;DAT
t
SUB ADDR
R
WR
t
SU;DAT
Figure 9. Slave Address Configuration
Figure 12. I
Figure 13. I
P = STOP BIT
A(M) = ACKNOWLEDGE BY MASTER
Figure 10. I
Figure 11. I
0
ACK
A(S)
Rev. PrA | Page 12 of 33
t
SUB ADDR
HIGH
SUB ADDRESS
t
S
F
2
2
0
2
C Data Transfer Timing
C Port Timing Diagram
2
A7
C Write Data Transfer
SLAVE ADDR, LSB = 1 (RD)
C Read Data Transfer
SUB ADDR[6...1]
t
SU;STA
A(S)
0
DATA
S
0
A0
A(S)
A(M) = LACK OF ACKNOWLEDGE BY MASTER
t
SU;STO
t
A(S) DATA A(M)
HD;STA
ACK
0
DATA
D7
R/W
CTRL.
0 = WR
1 = RD
Preliminary Technical Data
P
DATA
X
A(S)
DATA[6...1]
t
BUF
t
R
P
S
DATA
A(M)
D0
P
ACK
STOP BIT
P

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