IR3513Z International Rectifier Corp., IR3513Z Datasheet - Page 12

• Manufacturer Part Number: IR3513Z
• Description: Xphase3tm Pol Control Ic
• Manufacturer: International Rectifier Corp.

SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the XPhase
trailing edge modulation is used. A voltage-type error amplifier with high-gain (110dB) and wide-bandwidth is used for
the control loop. It is not unity gain stable. The power-stage input voltage is sensed by the IR3513Z, and optional phase
ICs, to provide feed-forward control. The PWM ramp slope will change with the input voltage and automatically
compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output
voltage or due to the wire and PCB-trace voltage drop related to changes in load current.
Frequency and Phase Timing Control
The oscillator system clock frequency is programmable from 500 kHz to 9 MHZ by an external resistor. The IR3513Z
system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is
controlled by the daisy chain loop, where the IR3513Z phase clock output (PHSOUT) is connected to the phase clock
input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC,
etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the
the IR3513Z sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to
determine the phase number and monitor any fault in the daisy chain loop. Figure 4 shows the phase timing for a four-
phase converter. For single-phase operation, PHSOUT (pin 26) and PHSIN (pin 27) must be shorted together to
prevent an Open Control Loop fault from occurring.
Page 12
VOSNS+
VO
RFB1
CFB
VOSNS-
REMOTE SENSE
AMPLIFIER
RFB
FB
CLOCK GENERATOR
ERROR
AMPLIFIER
RCOMP
CCOMP
CCOMP1
VREF
IR3513 CONTROL IC
+
-
Control Bus to
additional Phases
TM
architecture is shown in Figure 3. Feed-forward voltage mode control with
Figure 3 - PWM Block Diagram
PHSOUT
ISHARE
DACIN
CLKIN
PHSIN
EAIN
3K
3K
CLK
D
CLK
D
SHARE ADJUST
ERROR AMPLIFIER
SHARE ADJUST
ERROR AMPLIFIER
Q
Q
+
-
+
-
RAMP
DISCHARGE
CLAMP
RAMP
DISCHARGE
CLAMP
ENABLE
ENABLE
PWM
COMPARATOR
-
PWM
COMPARATOR
-
VID6
VID6
+
+
VID6
VID6
VID6
VID6
-
+
-
+
+
-
+
-
PHASE IC
BODY
BRAKING
COMPARATOR
BODY
BRAKING
COMPARATOR
PWM
LATCH
DOMINANT
PWM
LATCH
DOMINANT
S
RESET
R
S
RESET
R
VID6
VID6
VID6
VID6
+
+
+
+
CURRENT
SENSE
AMPLIFIER
CURRENT
SENSE
AMPLIFIER
+
-
+
-
CSIN-
CSIN-
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CSIN+
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CSIN+
CCS
CCS
RCS
RCS
CBST
CBST
Power Bus to
additional Phases
May 11, 2009
loop.
IR3513Z
COUT
During power up,
VIN
IC BIAS
REMOTE SENSE +
VOUT
GND
REMOTE SENSE -