IR3513Z International Rectifier Corp., IR3513Z Datasheet - Page 20

• Manufacturer Part Number: IR3513Z
• Description: Xphase3tm Pol Control Ic
• Manufacturer: International Rectifier Corp.

IR3513Z
VCCL Under Voltage Lockout (UVLO)
The IR3513Z IC monitors both the Vcc and VCCL for under voltage condition. During power up, the fault latch will be
reset if VCCL is above 94% (typical) of the voltage set by resistor divider at VCCLFB pin and the VCC exceeds 7.5V
(typical). If VCCL voltage drops below 86% (typical) of the set value or VCC drops below 7V (typical), the fault latch will
be set.
Power Good (PG)
The PG pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft start,
the PG remains low until the output voltage is in regulation and SS/DEL is above 3.12V. The PG pin becomes low if the
fault latch, over voltage latch, open sense line latch, or open daisy chain latch is set. A high level at the PG pin indicates
that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification.
Output voltage regulation within the design limits can logically be assured however, assuming no component failure in
the system.
Open Voltage Loop Detection
The output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. If any fault
condition forces the error amplifier output above VCCL-0.3V for 8 switching cycles, the fault latch is set. The fault latch
can only be cleared by cycling power to VCCL.
Load Current Indicator Output
The IIN pin voltage represents the average current of the converter plus the VREF voltage. The load current information
can be retrieved by a differential amplifier which subtracts the VREF voltage from the IIN voltage.
Enable Input
Pulling the ENABLE pin below 0.8V sets the Fault Latch and a voltage above 0.85V enables the soft start of the
converter.
Over Voltage Protection (OVP)
Output over-voltage can occur during normal operation if a high side MOSFET short or other failure occurs. The over-
voltage protection comparator monitors the OVSNS pin voltage. If the OVSNS pin voltage exceeds VREF by 85mV, as
shown in Figure 11, the ROSC/OVP pin voltage is driven to V(VCCL) - 1V sending an over voltage signal to the host
system. The ROSC/OVP pin can also be connected to a crowbar circuit, which pulls the converter input low in over
voltage conditions.
The over voltage condition also sets the over voltage fault latch, which pulls the error amplifier output low to turn off the
converter output. At the same time IIN pin (ISHARE of phase ICs) is pulled up to VCCL to communicate the over
voltage condition to phase ICs (if present), as shown in Figure 11. The OVP circuit overrides the normal PWM operation
and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain on until
ISHARE pin voltage drops below V(VCCL) - 800mV, which signals the end of over voltage condition. An over voltage
fault condition is latched in the IR3513Z and can only be cleared by cycling power to VCCL.
In the event of a high side MOSFET short before power up, the OVP flag is activated with as little supply voltage as
possible, as shown in Figure 12. The OVSN pin is compared against a fixed voltage of 1.73V (typical) for OVP
conditions at power-up. The ROSC/OVP pin will be pulled higher than 1.6V with VCCLDRV voltage as low as 1.8V. An
external MOSFET or comparator should be used to disable the silver box, activate a crowbar, or turn off the supply
source. The 1.8V threshold is used to prevent false over-voltage triggering caused by pre-charging of output capacitors.
Page 20
May 11, 2009