IR3513Z International Rectifier Corp., IR3513Z Datasheet - Page 32

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IR3513Z

Manufacturer Part Number
IR3513Z
Description
Xphase3tm Pol Control Ic
Manufacturer
International Rectifier Corp.
Datasheet

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LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane.
• Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce
• Connect PGND to LGND pins to the ground plane through vias
• Place current sense resistors and capacitors (R
• Place the IC, gate drive side as close as possible to the MOSFETs to reduce the parasitic resistance and
• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET.
the noise coupling.
current sense wires, but separate the two wires by ground polygon. The wire from the inductor terminal to
CSIN- should not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs and bootstrap
nodes.
inductance of the gate drive paths.
Page 32
CS
and C
CS
) close to IC. Use Kelvin connection for the inductor
May 11, 2009
IR3513Z

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