MBM29DL161TE-70TN Meet Spansion Inc., MBM29DL161TE-70TN Datasheet - Page 42

• Manufacturer Part Number: MBM29DL161TE-70TN
• Description: Flash Memory Cmos 16m 2m ? 8/1m ? 16 Bit Dual Operation
• Manufacturer: Meet Spansion Inc.

42
MBM29DL16XTE/BE
Toggle Bit I
Exceeded Timing Limits
driving status information on DQ
Depending on when the system samples the DQ
has completed the Embedded Algorithm operation and DQ
may be still invalid. The valid data on DQ
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags Table”.)
See “(6) AC Waveforms for Data Polling during Embedded Algorithm Operations” in ■TIMING DIAGRAM for
the Data Polling timing specifications and diagrams.
• DQ
The MBM29DL16XTE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the devices will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 μs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
cause the DQ
The system can use DQ
is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ
Erase Suspend mode, DQ
DQ
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See “(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the
Toggle Bit I timing specifications and diagrams.
• DQ
DQ
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in “MBM29DL16XTE/BE User Bus
Operations Tables (BYTE = V
The DQ
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
6
5
to toggle.
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
6
5
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
6
to toggle.
5
will produce a “1”. This is a failure condition which indicates that the program or erase
6
6
will stop toggling and valid data will be read on the next successive attempts. During
7
to determine whether a sector is actively erasing or is erase-suspended. When a bank
bit and DQ
6
stops toggling. Successive read cycles during the erase-suspend-program cause
IH
6
and BYTE = V
7
toggling between “1” and “0”. Once the Embedded Program or Erase Algorithm
at one instant of time and then that byte’s valid data at the next instant of time.
Retired Product DS05-20880-5E_July 13, 2007
6
never stops toggling. Once the devices have exceeded timing limits, the
7
70/90
to DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
IL
)” in ■DEVICE BUS OPERATION.
7
0
output, it may read the status or valid data. Even if the device
will be read on the successive read attempts.
7
has a valid data, the data outputs on DQ
6
toggles. When a bank enters the
6
to DQ
0