MBM29LV320TE Fujitsu Microelectronics, Inc., MBM29LV320TE Datasheet - Page 31

• Manufacturer Part Number: MBM29LV320TE
• Description: 32 M 4 M X 8/2 M X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

13. DQ
Data Polling
14. DQ
Toggle Bit I
15. DQ
Exceeded Timing Limits
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce a
complement of data last written to DQ
read device will produce true data last written to DQ
device will produce a “0” at the DQ
read device will produce a “1” on DQ
( FLOW CHART).
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased,
not a protected sectors. Otherwise, the status may be invalid.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
asynchronously while the output enable (OE) is asserted low. This means that the device is driving status
information on DQ
on when the system samples the DQ
the Embedded Algorithm operation and DQ
The valid data on DQ
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erase Suspend mode or sector erase time-out. (See “Hardware Sequence Flags” Table.)
See “6. Data Polling during Embedded Algorithm Operation Timing Diagram” in
Data Polling timing specifications and diagrams.
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the device will results in DQ
Algorithm cycle is completed, DQ
During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequence. The Toggle Bit I is active during the sector time out.
In program operation, if the sector being written is protected, the toggle bit will toggle for about 1 s and then
stop toggling with data unchanged. In erase operation, the device will erase all selected sectors except for ones
that are protected. If all selected sectors are protected, chip will toggle the toggle bit for about 400 s and then
drop back into read mode, having data unchanged.
Either CE or OE toggling will cause DQ
See “7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in
Toggle Bit I timing specifications and diagrams.
DQ
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of device under this condition.
The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and
5
7
6
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
7
at one instant of time and then that byte’s valid data at the next instant of time. Depending
5
0
will produce a “1”. This is a failure condition which indicates that the program or erase
to DQ
7
will be read on the successive read attempts.
6
6
will stop toggling and valid data will be read on the next successive attempts.
7
7
7
toggling between one and zero. Once the Embedded Program or Erase
. The flowchart for Data Polling (DQ
output. Upon completion of the Embedded Erase Algorithm an attempt to
output, it may read the status or valid data. Even if the device has completed
7
. Upon completion of the Embedded Program Algorithm, an attempt to
6
to toggle.
7
has a valid data, the data outputs on DQ
7
. During the Embedded Erase Algorithm, an attempt to read
MBM29LV320TE/BE
7
) is shown in “3. Data Polling Algorithm”
0
TIMING DIAGRAM for the
TIMING DIAGRAM for the
to DQ
6
may be still invalid.
7
) may change
80/90/10
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