MBM29LV320TE Fujitsu Microelectronics, Inc., MBM29LV320TE Datasheet - Page 34

• Manufacturer Part Number: MBM29LV320TE
• Description: 32 M 4 M X 8/2 M X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

34
MBM29LV320TE/BE
22. Low V
23. Write Pulse “Glitch” Protection
24. Logical Inhibit
25. Power-Up Write Inhibit
To avoid initiation of a write cycle during V
than V
disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the
V
prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Noise pulses of less than 3 ns (Typ) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE
must be a logical zero while OE is a logical one.
Power-up of the device with WE
The internal state machine is automatically reset to the read mode on power-up.
CC
level is greater than V
LKO
CC
(Min) . If V
Write Inhibit
CC
LKO
V
LKO
. It is the users responsibility to ensure that the control pins are logically correct to
, the command register is disabled and all internal program/erase circuits are
CE
CC
is above V
80/90/10
V
CC
IL
and OE
power-up and power-down, a write cycle is locked out for V
V
LKO
IL
, CE
(Min) .
V
IH
V
will not accept commands on the rising edge of WE.
IH
, or WE
V
IH
. To initiate a write cycle CE and WE
CC
less