MBM29LV320TE Fujitsu Microelectronics, Inc., MBM29LV320TE Datasheet - Page 32

• Manufacturer Part Number: MBM29LV320TE
• Description: 32 M 4 M X 8/2 M X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

32
MBM29LV320TE/BE
16. DQ
Sector Erase Timer
17. DQ
Toggle Bit II
18. Reading Toggle Bits DQ
WE pins will control the output disable functions as described in “MBM29LV320TE/BE User Bus Operations
Tables (BYTE = V
The DQ
case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never
read valid data on DQ
bit will indicate a “1.” Please note that this is not a device failure condition since device was incorrectly used. If
this occurs, reset device with command sequence.
After completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or Toggle Bit I indicates device has been written with a valid erase command, DQ
to determine if the sector erase timer window is still open. If DQ
has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is
completed as indicated by Data Polling or Toggle Bit I. If DQ
erase commands. To insure the command has been accepted, the system software should check the status of
DQ
check, the command may not have been accepted.
See “Hardware Sequence Flags Table”.
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows :
For example, DQ
(DQ
Furthermore, DQ
mode, DQ
Whenever the system initially begins reading toggle bit status, it must read DQ
determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation.
The system can read array data on DQ
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If
it is still toggling, the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data.
3
6
2
3
2
prior to and following each subsequent Sector Erase command. If DQ
is different from DQ
toggles while DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
2
toggles if this bit is read from an erasing sector.
2
2
IH
and DQ
can also be used to determine which sector is being erased. When the device is in the erase
and BYTE = V
6
7
does not.) See also “Toggle Bit Status Table” and “8. DQ
bit and DQ
2
6
in that DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
/DQ
2
6
, can be used to determine whether the device is in the Embedded Erase
IL
6
)” ( DEVICE BUS OPERATIONS).
never stop toggling. Once the device has exceeded timing limits, the DQ
6
toggles only when the standard program or Erase, or Erase Suspend
7
80/90/10
to DQ
5
is high (see “15. DQ
0
on the following read cycle.
2
to toggle during the Embedded Erase Algorithm. If the
3
is low (“0”) , the device will accept additional sector
3
is high (“1”) the internally controlled erase cycle
5
”) . If it is the system should then determine
2
bit.
3
2
7
were high on the second status
vs DQ
to DQ
6
0
” in TIMING DIAGRAM.
at least twice in a row to
7
, is summarized
3
may be used
5
went high.
3
will
5
2