MBM29DL640E Fujitsu Microelectronics, Inc., MBM29DL640E Datasheet
MBM29DL640E
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MBM29DL640E Summary of contents
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... Dual Operation MBM29DL640E DESCRIPTION The MBM29DL640E M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 Mwords of 16 bits each. The device is offered in 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed to be programmed in system with 3 operations. The device can also be reprogrammed in standard EPROM programmers. ...
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... MBM29DL640E 80/90/12 (Continued) In the device, a new design concept called FlexBank device can execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and Bank 2, a bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1. ...
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... increases program performance ACC • Embedded Erase TM Algorithms Automatically preprograms and erases the chip or any sector • Embedded Program TM Algorithms Automatically writes and verifies data at specified address MBM29DL640E 15) 15) 2 PROMs Normal Bend Type, TR Reversed Bend Type) 80/90/12 (Continued) 3 ...
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... MBM29DL640E 80/90/12 (Continued) • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, the device automatically switches itself to low power mode. ...
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... RESET MBM29DL640E TSOP ( (Marking Side) BYTE Standard Pinout ...
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... MBM29DL640E 80/90/12 (Continued N.C. N. N.C. N. RESET A C4 RY/BY WP/ACC N. N.C. N.C. 6 FBGA (TOP VIEW) (Marking Side BYTEDQ ...
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... PIN DESCRIPTIONS Table 1 MBM29DL640E Pin Configuration Pin Address Input Data Input/Output Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Group Unprotection BYTE Selects 8-bit or 16-bit mode WP/ACC Hardware Write Protection/Program Acceleration ...
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... MBM29DL640E 80/90/12 BLOCK DIAGRAM Bank A address State RESET Control WE Status CE & OE Command BYTE Control Register WP/ACC Bank D address LOGIC SYMBOL 8 Cell Matrix 8 Mbit (Bank A) X-Decoder Bank B Address RY/BY Bank C Address X-Decoder Cell Matrix 8 Mbit (Bank ...
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... DEVICE BUS OPERATION Table 2 MBM29DL640E User Bus Operations (BYTE Operation Auto-Select Manufacturer L 1 Code * Auto-Select Device Code * Extended Auto-Select Device Code * 1 L Read * 3 L Standby H Output Disable L Write (Program/Erase) L Enable Sector Group L Protection * Verify Sector Group Protection ...
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... MBM29DL640E (Continued) Table 3 MBM29DL640E User Bus Operations (BYTE Operation Auto-Select Manufacturer Code * Auto-Select Device L L Code * Extended Auto-Select Device Code * Read * L L Standby H X Output Disable L H Write (Program/Erase Enable Sector Group L V Protection * Verify Sector Group ...
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... Table 4 MBM29DL640E Command Definitions Bus First Bus Write Command Write Cycle Cy- Sequence cles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Word Read/ 1 XXXh F0h Reset Byte 555h Word Read/ 3 AAh Reset Byte AAAh 555h ...
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... MBM29DL640E (Continued) Bus First Bus Write Command Write Cycle Cy- Sequence cles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 555h Word Hi-ROM 3 Entry Byte AAAh Word 555h Hi-ROM 4 Program * 3 Byte AAAh Word 555h Hi-ROM 4 Exit * ...
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... Table 5.1 MBM29DL640E Sector Group Protection Verify Autoselect Codes Type Manufacture’s Code BA *3 Byte Device Code BA *3 Word Byte BA *3 Word Extended Device Code *4 Byte BA *3 Word Sector Group Sector Group Protection Addresses * for Byte mode Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. ...
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... MBM29DL640E FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Sec- Bank Bank tor Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 ...
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... SA49 SA50 SA51 SA52 SA53 MBM29DL640E Sector Size Address Range / (Kbytes Kwords 64/32 100000h to 10FFFFh 080000h to 087FFFh 64/32 110000h to 11FFFFh 088000h to 08FFFFh ...
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... MBM29DL640E (Continued) Sector Address Sec- Bank Bank tor Address SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 Bank SA62 ...
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... SA98 SA99 SA100 SA101 SA102 MBM29DL640E Sector Size Address Range / (Kbytes Kwords 64/32 400000h to 40FFFFh 200000h to 207FFFh 64/32 410000h to 41FFFFh 208000h to 20FFFFh 1 ...
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... MBM29DL640E (Continued) Sector Address Sec- Bank Bank tor Address SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 Bank C SA111 SA112 1 ...
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... SA139 SA140 SA141 Note : The address range The address range MBM29DL640E Sector Size Address Range / (Kbytes Kwords 64/32 700000h to 70FFFFh 380000h to 387FFFh ...
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... MBM29DL640E Sector Group SGA0 0 0 SGA1 0 0 SGA2 0 0 SGA3 0 0 SGA4 0 0 SGA5 0 0 SGA6 0 0 SGA7 0 0 SGA8 0 0 SGA9 0 0 SGA10 0 0 SGA11 0 0 SGA12 0 0 SGA13 0 0 SGA14 0 0 SGA15 0 0 SGA16 0 1 SGA17 0 1 SGA18 ...
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... SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 MBM29DL640E ...
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... MBM29DL640E Table 8 Common Flash Memory Interface Code Description Query-unique ASCII string “QRY” Primary OEM Command Set 2h : AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h not applicable) Address for Alternate OEM Extended Table V Min. (write/erase D3-0 : 100 mV V Max ...
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... For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D. MBM29DL640E Table 9 FlexBank TM ...
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... MBM29DL640E Case writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D ...
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... WE or CE, whichever happens later, while data is latched on the rising edge CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. MBM29DL640E active current ( required. ...
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... MBM29DL640E Sector Group Protection The device features hardware sector group protection. This feature will disable both program and erase opera- tions in any combination of forty eight sector groups of memory. (See Table 7) . The user‘s side can use the sector group protection using programming equipment. The device is shipped with all sector groups that are unprotected ...
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... Kbytes on both ends of boot sectors independently of whether those sectors are protected or unprotected using the method described in “Sector Protection/Unprotection.” (MBM29DL640E : SA0, SA1, SA140, and SA141) If the system asserts V on the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte on both IH ends of boot sectors were last set to be protected or unprotected ...
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... MBM29DL640E COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are input into a bank reading, the commands have priority over the reading. Table 4 shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress ...
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... Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence, the device will automatically program and verify the entire memory for an all- MBM29DL640E (Data Polling ...
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... MBM29DL640E zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence, and terminates when the data on DQ device returns to the read mode ...
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... “0” in word mode (16 bit) read. Refer to CFI code table (Table 12 terminate operation necessary to write the read/reset command sequence into the register. MBM29DL640E bit will be at logic “1”, and and DQ to determine if the erase operation has been ...
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... MBM29DL640E Hidden ROM (Hi-ROM) Region The Hi-ROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modifi- cation of that region becomes impossible ...
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... DQ is limited to Fujitsu internal use. 4 MBM29DL640E will not toggle if an address from a non-erasing sector is consecutively 2 , the DQ toggles in the case of [1] and [3]. In case of [2], the data 6 is toggled in [1] and [3]. In case of [2], the data of memory cell is output. ...
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... MBM29DL640E DQ 7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a complement of data last written to DQ read the device will produce true data last written to DQ read the device will produce a “ ...
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... the following read cycle MBM29DL640E never stop toggling. Once the device has exceeded timing limits, the high (“1”) the internally controlled erase 3 were high on the second status check, the command may not have ...
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... MBM29DL640E However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ went high ...
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... Writing is inhibited by holding any one of OE must be a logical zero while logical one. Power-Up Write Inhibit Power-up of the device with WE The internal state machine is automatically reset to the read mode on power-up. MBM29DL640E power-up and power-down, a write cycle is locked out for above V (Min.) . ...
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... OE and RESET pins is 0.5 V. During voltage transitions 2.0 V for periods ns. Voltage difference between input does not exceed 9.0 V. Maximum DC input voltage 0.5 V. During voltage transitions, WP/ACC pin may Part No. MBM29DL640E 80 MBM29DL640E 90/12 MBM29DL640E 80 CC MBM29DL640E 90/12 Rating Unit Min. Max. 55 125 0.5 V ...
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... MAXIMUM OVERSHOOT/UNDERSHOOT 0.6 V 0.5 V 2.0 V Figure 1 Maximum Undershoot Waveform 2.0 V Figure 2 Maximum Overshoot Waveform 1 14 Note : This waveform is applied for A9, OE and RESET. Figure 3 Maximum Overshoot Waveform 2 MBM29DL640E 80/90/12 39 ...
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... MBM29DL640E ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Input Leakage Current Output Leakage Current A , OE, RESET Inputs Leakage 9 Current WP/ACC Accelerated Program Current V Active Current * Active Current * Current (Standby Current (Standby, Reset Current CC (Automatic Sleep Mode Active Current * ...
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... CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE to BYTE Switching Low or High Note : Test Conditions : Output Load : 1 TTL gate and 30 pF (MBM29DL640E-80) 1 TTL gate and 100 pF (MBM29DL640E-90/120) Input rise and fall times : 5 ns Input pulse levels : 0 3.0 V Timing measurement reference level Input : 1 ...
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... MBM29DL640E • Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from High During Toggle Bit Polling Data Setup Time Data Hold Time Read Output ...
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... Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time *1: This does not include preprogramming time. *2: This timing is for Sector Group Protection operation. *3: This timing is for Accelerated Program operation. MBM29DL640E Symbol OESP ...
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... MBM29DL640E ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle TSOP (I) PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Note : Test conditions FBGA PIN CAPACITANCE ...
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... TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM Address OEH WE High-Z Outputs Figure 5.1 Read Operation Timing Diagram MBM29DL640E INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Change Change from from May Will Change Change from from "H" or "L": ...
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... MBM29DL640E Address RESET Outputs Figure 5.2 Hardware Reset/Read Operation Timing Diagram 46 80/90/ Address Stable t ACC High-Z Outputs Valid t OH ...
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... D is the output of the data written to the device. OUT 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the Figure 6 Alternate WE Controlled Program Operation Timing Diagram MBM29DL640E Data Polling WHWH1 t ...
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... MBM29DL640E Address Data Notes : address of the memory location to be programmed data to be programmed at word address the output of the complement of the data written to the device the output of the data written to the device. OUT 5. Figure indicates last two bus cycles out of four bus cycle sequence. ...
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... AAh Data t VCS the sector address for Sector Erase. Addresses Note : These waveforms are for the Figure 8 Chip/Sector Erase Operation Timing Diagram MBM29DL640E 2AAh 555h 555h 2AAh 55h 80h AAh 555h (Word) for Chip Erase. ...
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... MBM29DL640E Data Data BUSY RY/ Valid Data (The device has completed the Embedded operation Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram 50 80/90/ OEH WHWH1 Output Flag High Valid Data ...
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... Toggle DQ /DQ Data 6 2 Data t BUSY RY/ stops toggling (The device has completed the Embedded operation). 6 Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations MBM29DL640E ASO AHT AS t CEPH t OEH Stop Toggle Toggle Toggling Data Data ...
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... MBM29DL640E Read t RC Address BA1 GHWL WE Valid DQ Output Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 Figure 11 Bank-to-Bank Read/Write Timing Diagram Enter Erase Embedded Suspend Erasing WE Erase ...
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... CE WE RY/BY Figure 13 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET RY/BY Figure 14 RESET, RY/BY Timing Diagram MBM29DL640E The rising edge of the last WE signal Entire programming or erase operations t BUSY READY 80/90/12 53 ...
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... MBM29DL640E CE BYTE ELFH Figure 15 Timing Diagram for Word Mode Configuration CE BYTE t ELFL Figure 16 Timing Diagram for Byte Mode Configuration BYTE Figure 17 BYTE Timing Diagram for Write Operations 54 80/90/ Data Output ( ...
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... OE t VLHT WE t OESP t CSP CE Data t VCS V CC SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected Note : byte mode Figure 18 Sector Group Protection Timing Diagram MBM29DL640E t t VLHT VLHT t WPP 01h t OE 80/90/12 SPAY 55 ...
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... MBM29DL640E VIDR t VCS RESET CE WE RY/BY Figure 19 Temporary Sector Group Unprotection Timing Diagram 56 80/90/12 t Program or Erase Command Sequence VLHT Unprotection period t VLHT t VLHT ...
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... Data 60h SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window 250 s (Min.) Figure 20 Extended Sector Group Protection Timing Diagram MBM29DL640E t WC SPAX SPAX TIME-OUT 60h 40h 80/90/12 SPAY 01h 60h t OE ...
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... MBM29DL640E VCC t VACCR t VCS VACC V IH WP/ACC CE WE RY/BY Figure 21 Accelerated Program Timing Diagram 58 80/90/12 t VLHT Program or Erase Command Sequence Acceleration period t VLHT t VLHT ...
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... FLOW CHART EMBEDDED ALGORITHM Increment Address Note : The sequence is applied for The addresses differ from Figure 22 Embedded Program MBM29DL640E Start Write Program Command Sequence (See Below) Data Polling No Verify Data ? Yes No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command) 555h/AAh ...
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... MBM29DL640E EMBEDDED ALGORITHM Chip Erase Command Sequence (Address/Command) Note : The sequence is applied for The addresses differ from 60 80/90/12 Start Write Erase Command Sequence (See Below) Data Polling Embedded Erase Algorithm No in progress Data FFh ? Yes Erasure Completed Individual Sector/Multiple Sector Erase Command Sequence ...
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... No ( rechecked even if DQ “1” because Figure 24 Data Polling Algorithm MBM29DL640E VA Address for programming Any of the sector addresses within the sector being erased Start during sector erase or multiple erases operation. Read Byte Any of the sector addresses to DQ ...
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... MBM29DL640E *1 : Read toggle bit twice to determine whether or not it is toggling Recheck toggle bit because it may stop toggling 80/90/12 Start Read Addr Read Addr Toggle Bit Toggle? Yes Yes *1, 2 Read Twice Addr ...
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... Increment PLSCNT No PLSCNT Yes Remove V ID Write Reset Command Device Failed * : byte mode Figure 26 Sector Group Protection Algorithm MBM29DL640E Start Setup Sector Group Addr PLSCNT ...
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... MBM29DL640E *1 : All protected sectors are unprotected All previously protected sectors are reprotected. Figure 27 Temporary Sector Group Unprotection Algorithm 64 80/90/12 Start RESET Perform Erase or Program Operations RESET V IH Temporary Sector Group Unprotection Completed *2 ...
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... Read from Sector Group Address No (Addr PLSCNT 25? Yes Protect Other Sector Remove V from RESET ID Write Reset Command Remove V Write Reset Command Device Failed Sector Protection Figure 28 Extended Sector Group Protection Algorithm MBM29DL640E Start V ID Wait Yes ...
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... MBM29DL640E FAST MODE ALGORITHM Increment Address Notes: The sequence is applied for The addresses differ from Figure 29 Embedded Programming Algorithm for Fast Mode 66 80/90/12 Start 555h/AAh 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data Polling No Verify Data? Yes No Last Address? Yes Programming Completed (BA) ...
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... E 80 DEVICE NUMBER/DESCRIPTION MBM29DL640 64 Mega-bit (8 M 3.0 V-only Read, Program, and Erase Valid Combinations 80 MBM29DL640E 90 12 MBM29DL640E TN PACKAGE TYPE TN 48-Pin Thin Small Outline Package (TSOP) Standard Pinout TR 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PBT 63-Ball Fine pitch Ball Grid Array ...
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... MBM29DL640E PACKAGE DIMENSIONS 48-pin plastic TSOP (I) (FPT-48P-M19) LEAD No. 1 INDEX 24 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) 0.10(.004) 19.00±0.20 (.748±.008) 1996 FUJITSU LIMITED F48029S-2C 80/90/12 * Resin Protrusion. (Each Side : 0.15 (.006) Max) 48 Details of "A" part "A" 25 0.50(.0197) TYP 0.15± ...
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... INDEX 24 19.00±0.20 (.748±.008) 0.10(.004) 18.40±0.20 * (.724±.008) 20.00±0.20 (.787±.008) 1996 FUJITSU LIMITED F48030S-2C-2 C MBM29DL640E * Resin Protrusion. (Each Side : 0.15 (.006) Max) 48 Details of "A" part 0.15(.006) MAX "A" 0.15(.006) 0.25(.010) 25 0.50±0.10 (.020±.004) 0.15±0.10 0.20±0.10 (.006± ...
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... MBM29DL640E 63-ball plastic FBGA (BGA-63P-M02) 11.00±0.10(.433±.004) INDEX AREA 0.10(.004) 1999 FUJITSU LIMITED B63002S-1C 80/90/12 +0.15 1.05 –0.10 +.006 .041 –.004 (Mounting height) 0.38±0.10 (.015±.004) (Stand off) (4.00(.157)) 10.00±0.10 (.394±.004) (5.60(.220)) (8.80(.346)) (7.20(.283)) (5.60(.220)) 0.80(.031)TYP ...
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... MBM29DL640E 80/90/12 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. ...