MBM29DL640E Fujitsu Microelectronics, Inc., MBM29DL640E Datasheet - Page 24

• Manufacturer Part Number: MBM29DL640E
• Description: Flash Memory 64 M 8 M X 8/4 M X 16 Bit Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

24
MBM29DL640E
* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets
Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank
Read Mode
Standby Mode
suspended so that it enables reading from or programming the remaining sectors.
The device has two control functions which are required in order to obtain data at the outputs. CE is the power
control and should be used for a device selection. OE is the output control and should be used to gate data to
the output pins.
Address access time (t
time (t
access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses
have been stable for at least t
it is necessary to input hardware reset or to change CE pin from “H” or “L”
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET input held at V
this condition the current consumed is less than 5 A Max. During Embedded Algorithm operation, V
current (I
these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
the device requires t
During standby mode, the output is in the high impedance state, regardless of OE input.
“H” or “L”) . Under this condition the current consumed is less than 5 A Max. Once the RESET pin is set high,
consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the
Banks.
Case
CE
1
2
3
4
5
6
7
) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable
CC2
) is required even if CE
RH
ACC
as a wake-up time for output to be valid for read access.
) is equal to delay from stable addresses to valid output data. The chip enable access
ACC
80/90/12
-t
OE
Autoselect mode
Table 11 Simultaneous Operation
Bank 1 Status
Program mode
Erase mode *
time) . When reading out data without changing addresses after power-up,
Read mode
Read mode
Read mode
Read mode
“H”. The device can be read with standard access time (t
Autoselect mode
Bank 2 Status
Program mode
Erase mode *
Read mode
Read mode
Read mode
Read mode
CC
CE
) from either of
SS
0.3 V. Under
0.3 V (CE
CC
active