M25PX16 Numonyx, M25PX16 Datasheet
M25PX16
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M25PX16 Summary of contents
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... More than 100 000 write cycles per sector More than 20 year data retention Packages – ECOPACK® (RoHS compliant) August 2008 16-Mbit, dual I/O, 4-Kbyte subsector erase, Rev 2 M25PX16 VFQFPN8 (MP) 6 × SO8W (MW) 208 mils SO8 (MN) 150 mils 1/61 www ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Read Status Register (RDSR 6.4.1 ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M25PX16 Mbit ( serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX16 supports two new, high-performance dual input/output instructions: Dual Output Fast Read (DOFR) instruction used to read data MHz ...
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... There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See section for package dimensions, and how to identify pin-1. Package mechanical V CC DQ1 C M25PX16 Function M25PX16 DQ1 2 7 HOLD W ...
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Signal descriptions 2.1 Serial Data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the Dual Input Fast Program (DIFP) ...
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If the W/V input is kept in a low voltage range ( input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as ...
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... Serial Data output (DQ1) line at a time, the other devices are high impedance. Resistors R (represented in ensure that the M25PX16 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high ...
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Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 4. SPI modes supported CPOL CPHA ...
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Operating features 4.1 Page programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the ...
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Active Power, Standby Power and Deep Power-down modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX16 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification ...
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Write Lock and Lock Down bits cannot be performed. A power- up, is required before changes to these bits can be made. When the Lock Down bit is reset, ‘0’, the Write Lock and Lock Down bits ...
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Table 3. Protected area sizes Status Register contents bit bit 2 bit 1 bit The device is ready to accept a Bulk Erase instruction if, and only if, ...
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Figure 5. Hold condition activation C HOLD (standard use) Hold Condition (non-standard use) Hold Condition AI02029D 17/61 ...
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Memory organization The memory is organized as: 2 097 152 bytes (8 bits each) 512 subsectors (4 Kbytes each) 32 sectors (64 Kbytes each) 8192 pages (256 bytes each) 64 OTP bytes located outside the main memory array Each ...
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Table 4. Memory organization Sector Subsector Address range 511 1FF000h 31 496 1F0000h 495 1EF000h 30 480 1E0000h 479 1DF000h 29 464 1D0000h 463 1CF000h 28 448 1C0000h 447 1BF000h 27 432 1B0000h 431 1AF000h 26 416 1A0000h 415 19F000h ...
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Table 4. Memory organization (continued) Sector Subsector 159 9 144 143 8 128 127 7 112 111 20/61 Address range Sector 9F000h 9FFFFh 3 90000h 90FFFh 8F000h 8FFFFh 2 80000h 80FFFh 7F000h ...
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Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select (S) ...
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Table 5. Instruction set Instruction Read OTP (Read 64 bytes of ROTP OTP area) Program OTP (Program 64 POTP bytes of OTP area) PP Page Program DIFP Dual Input Fast Program SSE Subsector Erase SE Sector Erase BE Bulk Erase ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
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See Section 12: Ordering information on page 59 Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) ...
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Table 7. Status Register format b7 SRWD Status Register Write Protect The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a ...
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SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and the Write Protect PP (W/V ) signal allow the device to ...
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Write Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and Write PP Protect (W/V ) signal allow the device to be put in the hardware protected mode (HPM). PP The Write Status Register (WRSR) instruction is ...
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When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W/V If Write Protect (W/V provided that the Write Enable Latch ...
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Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence DQ0 High Impedance DQ1 1. Address bits A23 to A22 are Don’t care. 6.7 Read Data Bytes at higher speed (FAST_READ) The device is first ...
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Figure 13. Read Data Bytes at higher speed (FAST_READ) instruction sequence and data-out sequence DQ0 DQ1 DQ0 DQ1 1. Address bits A23 to A22 are Don’t care. 6.8 Dual ...
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When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. Figure 14. Dual Output Fast Read instruction sequence S Mode 3 C Mode 2 DQ0 DQ1 S ...
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Table 9. Lock Register out Bit Bit name b7-b2 b1 Sector Lock Down b0 Sector Write Lock 1. Values of (b1, b0) after power-up are defined in Figure 15. Read Lock Register (RDLR) instruction sequence and data-out sequence S 0 ...
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Erase, Program or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress. Figure 16. Read OTP (ROTP) instruction and data-out sequence DQ0 High ...
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If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to ...
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Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. ...
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Figure 18. Dual Input Fast Program (DIFP) instruction sequence DQ0 DQ1 DQ0 DATA DQ1 MSB 1. A23 to A22 are Don't care. ...
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Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program OTP cycle, and when it is completed. At some unspecified time ...
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Figure 20. How to permanently lock the 64 OTP bytes Byte Byte Byte 6.14 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it ...
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Table 10. Lock Register in Sector All sectors 1. Values of (b1, b0) after power-up are defined in 6.15 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. Before it can ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase ...
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Chip Select (S) is driven High, it requires a delay and the Deep Power-down mode is entered. CC2 Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without ...
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Figure 26. Release from Deep Power-down (RDP) instruction sequence Instruction DQ0 High Impedance DQ1 RDP Deep Power-down mode Standby mode AI13745 43/61 ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay ...
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Figure 27. Power-up timing (max) Program, Erase and Write commands are rejected by the device Chip Selection not allowed V CC (min) Reset state of the device V WI Table 11. Power-up timing and V Symbol ...
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Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 46/61 ...
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... V Electrostatic discharge voltage (Human Body model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 16. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 Operating current (READ) I CC3 Operating current (DOFR) Operating current (PP) I CC4 Operating current ...
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Table 17. AC characteristics Symbol Alt active hold time (relative to C) CHSH t S not active setup time (relative to C) SHCH deselect time SHSL CSH ( Output Disable time SHQZ DIS ...
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When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256). 9. int(A) corresponds to ...
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Expressed as a slew-rate. 5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. Figure 29. Serial input timing S tCHSL C tDVCH DQ0 DQ1 Figure 30. Write Protect Setup and Hold timing ...
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Figure 31. Hold timing S C DQ1 DQ0 HOLD Figure 32. Output timing S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN tHLCH tCHHL tCHHH tHLQZ tHHQX tCH tCLQV tCL tQLQH tQHQL tHHCH AI13746 tSHQZ LSB OUT AI13729 53/61 ...
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Figure 33. V PPH S C DQ0 V PPH V PP 54/61 timing BE tVPPHSL End of BE (identified by WIP polling) ai13726 ...
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... JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an Numonyx trademark. ECOPACK specifications are available at: www.numonyx.com. Figure 34. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × ...
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Table 19. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data Symbol Typ R1 0.10 L 0.60 Θ aaa bbb ddd Figure 35. SO8W 8-lead plastic small outline, 208 mils ...
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Table 20. SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data Millimeters Symbol Typ Min E1 7. 0.50 N Figure 36. SO8N – 8 lead plastic small outline, 150 mils body width, package ...
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Table 21. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol Typ e 1. 1.04 58/61 millimeters Min Max Typ – – 0.050 0.25 0.50 0° 8° 0.40 1.27 0.041 ...
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... Secure options are available upon customer request. 2. Grade 3 is available only in devices delivered in SO8N packages. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. M25PX16 – ...
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Revision history Table 23. Document revision history Date Revision 12-Aug-2008 0.1 27-Aug-2008 0.2 60/61 Changes Initial release. Corrected bulk erase specifications on the cover page; Changed Vwi from 2 2 due to 2.3 V operations; ...