M25PX16 Numonyx, M25PX16 Datasheet - Page 21

• Manufacturer Part Number: M25PX16
• Description: 16-mbit, Dual I/o, 4-kbyte Subsector Erase, Serial Flash Memory With 75 Mhz Spi Bus Interface
• Manufacturer: Numonyx

6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C)
after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to
the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ),
Dual Output Fast Read (DOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read
Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-down
(RDP) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted
out.
In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program
(DIFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register
(WRSR), Write to Lock Register (WRLR), Write Enable (WREN), Write Disable (WRDI) or
Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses after Chip Select (S) being driven Low is
an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 5.
FAST_READ
Instruction
WREN
WRSR
WRLR
RDSR
DOFR
RDLR
READ
WRDI
RDID
Instruction set
Write Enable
Write Disable
Read Identification
Read Status Register
Write Status Register
Write to Lock Register
Read Lock Register
Read Data Bytes
Read Data Bytes at higher
speed
Dual Output Fast Read
Description
Table
5.
One-byte instruction
0000 0100
0000 0101
0000 0001
0000 0110
1001 1110
1110 0101
1110 1000
0000 0011
0000 1011
0011 1011
1001 1111
code
9Fh
9Eh
E5h
E8h
0Bh
3Bh
06h
04h
05h
01h
03h
Address
bytes
0
0
0
0
0
0
3
3
3
3
3
Dummy
bytes
0
0
0
0
0
0
0
0
0
1
1
1 to 20
bytes
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to 3
Data
0
0
1
1
1
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