STPC STMicroelectronics, STPC Datasheet - Page 11

• Manufacturer Part Number: STPC
• Description: PC Compatible Embeded Microprocessor
• Manufacturer: STMicroelectronics

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Table 2-2. Definition of Signal Pins
BASIC CLOCKS AND RESETS
SYSRSTI#
XTALI
XTALO
HCLK
DEV_CLK
GCLK2X
DCLK
PCI_CLKI
PCI_CLKO
SYSRSTO#
ISA_CLK
ISA_CLK2X
MEMORY INTERFACE
MA[11:0]
RAS#[3:0]
CAS#[7:0]
MWE#
MD[63:0]
PCI INTERFACE
AD[31:0]
CBE[3:0]
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
PAR
SERR#
LOCK#
PCIREQ#[2:0]
PCIGNT#[2:0]
PCI_INT[3:0]
VDD5
ISA AND IDE COMBINED ADDRESS/DATA
LA[23:22] / SCS3#,SCS1#
LA[21:20] / PCS3#,PCS1#
LA[19:17] / DA[2:0]
RMRTCCS# / DD[15]
KBCS# / DD[14]
RTCRW# / DD[13]
RTCDS# / DD[12]
SA[19:8] / DD[11:0]
SA[7:0]
SD[15:0]
Signal Name
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
System Reset / Power good
14.3MHz Crystal Input
14.3MHz Crystal Output - External Oscillator Input
Host Clock (Test)
24MHz Peripheral Clock (floppy drive)
80MHz Graphics Clock
135MHz Dot Clock
33MHz PCI Input Clock
33MHz PCI Output Clock (from internal PLL)
Reset Output to System
ISA Clock Output - Multiplexer Select Line For IPC
ISA Clock x 2 Output - Multiplexer Select Line For IPC
Memory Address
Row Address Strobe
Column Address Strobe
Write Enable
Memory Data
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
Target Ready
Initiator Ready
Stop Transaction
Device Select
Parity Signal Transactions
System Error
PCI Lock
PCI Request
PCI Grant
PCI Interrupt Request
5V Power Supply for PCI ESD protection
Unlatched Address (ISA) / Secondary Chip Select (IDE)
Unlatched Address (ISA) / Primary Chip Select (IDE)
Unlatched Address (ISA) / Address (IDE)
ROM/RTC Chip Select / Data Bus bit 15 (IDE)
Keyboard Chip Select / Data Bus bit 14 (IDE)
RTC Read/Write / Data Bus bit 13 (IDE)
RTC Data Strobe / Data Bus bit 12 (IDE)
Latched Address (ISA) / Data Bus (IDE)
Latched Address (IDE)
Data Bus (ISA)
Issue 1.2
Description
PIN DESCRIPTION
Qty
12
64
32
16
16
1
1
1
1
1
1
1
1
1
1
1
1
4
8
1
4
1
1
1
1
1
1
1
1
3
3
4
4
2
2
3
1
1
1
1
4
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